1. Layered Protocol Wrappers Design and Interface review
James Moscola
Washington University
August 26, 2002
Abstract
By incorporating Field Programmable Gate Arrays (FPGAs) at the edge of a network switch, it is possible to implement hardware-based modules that have both the flexiblity to be reconfigured and the performance to process packets at the full rate of the Internet backbone. The Field Programmable Port Extender (FPX) has been built to augment an existing Gigabit switch systems with reprogrammable hardware modules. The FPX system includes a high-speed network interface, multiple banks of memory, and FPGA logic. The FPX allows hardware modules to be dynamically installed into the router by using partial reprogramming of an FPGA. Applications have been developed for the FPX that include IP packet routing, queuing, and data compression.

2. Layout of Protocol Wrappers with MAC circuit
Frames
MAC
Frames
MAC Egress
MAC Ingress
ATM
Cells
ATM
Cells
Cell Wrapper +
Frame Wrapper

3. The Cell Processor Cell Functions Flow Functions
Drops cells with bad cell headers
Recomputes cell header for outgoing cells (MAC Ingress side)
Flow Functions
Bypasses cells for different flows
Implements Control-Plane Interface
Handles control cells
Write control / read status

4. The Cell Processor Data Flow inside the Cell Processor MAC Frames
MAC Egress
MAC Ingress
VCI = 32 – 35h
Frame
Processor
and
MAC circuit
ATM
Cells
HEC
Dispatch
Check
VCI = 23h
All other VCIs
HEC
ATM
Cells
Set
Control
Cells
The output FIFOs are serviced in the following order:
Controls Cells
Bypassed Cells
Application Cells

5. The Frame Processor Segmentation and Reassembly Frame Functions
Reassembles cells into frames (MAC egress)
Segments frames into cells (MAC ingress)
Frame Functions
Detects frame boundaries
Checks & Generates AAL5 CRC

6. The Frame Processor Data Flow inside the Frame Processor MAC Egress
MAC Ingress
MAC
Frames
ATM
Cells
ATM
Cells
MAC circuit
Cell
Frame
AAL5CRC
Segment
AAL5CRC
Detection
ation

7. The Frame Processor
Module Details

8. The Frame Processor Frame Detection Module (MAC Egress)
Single Cell Frame
Buffers cell while waiting for length
Once length is received outputs appropriate number of words to the MAC Egress circuit
Multiple Cell Frame (cells A and B)
If not the last cell (PTI=‘0’), outputs all but last two words in cell A to MAC Egress circuit (the last two words my be padding)
if cell B PTI=‘0’, the last two words of cell A are output along with all but the last two words of the cell B
if cell B PTI=‘1’, cell B is buffered until the length is reached. Once the length is reached, it can be determined whether or not the last two words of cell A should be output to the MAC Egress circuit and how many words of cell B should be output to the MAC Egress circuit

9. The Frame Processor Cell Segmentation Module (MAC Ingress) Two FIFOs
data_fifo
written to whenever SOF_APPL_IN or DataEn_APPL_IN is asserted by MAC Ingress circuit
length_fifo
written to when…
a cells worth of data has been put into the data_fifo
EOF_APPL_IN has been asserted
Cells are output as long as the length_fifo has data
dequeue length_fifo and output that many words from the data_fifo
should always be 48 bytes, except for the last cell, when it should be <= 48 bytes

10. The Frame Processor
Interface Details

11. The Frame Processor Frame Interface (MAC Egress) SOF_OUT_APPL
high for 1 clock cycle during first ATM header word
signals start of new AAL5 frame
NOTE: HEC is NOT sent after this signal
DataEn_OUT_APPL
high during valid payload data (not during sof)
high during EOF_OUT_APPL and 2 AAL5 trailer words
D_OUT_APPL
32-bit data bus
EOF_OUT_APPL
high during 1 clock cycle of last payload word in AAL5 frame
followed by two trailer words of AAL5 frame
if no EOF_OUT_APPL is asserted for a frame (consecutive SOF_OUT_APPLs without an EOF_OUT_APPL), the frame is corrupt and should be discarded/handled by the application
TCA_OUT_APPL
this signal is passed through, it does not affect the behavior of the wrapper

12. The Frame Processor Frame Interface (MAC Egress) cont …
A frame with an invalid AAL5 CRC …
will be passed from the Frame Processor to the MAC Egress circuit
will have an EOF_OUT_APPL
will have a non-zero value in the AAL5 CRC field
Cells dropped from Multi-cell Frames
if a cell is dropped prior to entering the Frame wrapper, the frame will have an invalid AAL5 CRC and should be dropped. If the dropped cell is the last cell in the frame, both the current frame and the next frame will be combined with an invalid AAL5 CRC and should be dropped.

13. The Frame Processor Frame Interface (MAC Ingress) SOF_APPL_IN
must assert high for 1 clock cycle while outputting first ATM header word
NOTE: DO NOT send a HEC, as the HEC word is inserted by the Frame Wrapper
DataEn_APPL_IN
assert high during valid payload data (not during sof)
assert high during EOF_OUT_APPL and 2 AAL5 trailer words
D_APPL_IN
32-bit data bus
EOF_APPL_IN
assert high during 1 clock cycle of last payload word in AAL5 frame
this interface assumes a user application is following the interface protocol. If no EOF_APPL_IN is sent for a frame, it is possible for the 2 FIFOs to get out of synch and enter an unknown state
TCA_APPL_IN
this signal is passed through the wrapper to the user application. An application should stop sending data when TCA_APPL_IN is deasserted

14. The Frame Processor Frame Interface (MAC Ingress) cont …
bytes(1 downto 0) of the AAL5 Length field must be set to the number of valid bytes in the last payload word. Other bytes of the AAL5 Length can be ignored, as they will be calculated by the frame wrapper
If an application wants a frame to be dropped, any non-zero value can be inserted into the AAL5 CRC field. The frame will still be transmitted, but will get dropped at the next hop.

15. The Frame Processor