1. Chapter 3 – Combinational Logic Design
Logic Circuit Design
Chapter 3 – Combinational Logic Design

2. Overview Part 1 – Design Procedure Overview Steps
Specification
Formulation
Optimization
Technology Mapping
Beginning Hierarchical Design
Technology Mapping - AND, OR, and NOT to NAND or NOR
Verification
Manual
Simulation

3. Overview (continue) Part 2 – Combinational Logic Overview
Functions and functional blocks
Rudimentary logic functions
Decoding using Decoders
Implementing Combinational Functions with Decoders
Encoding using Encoders
Selecting using Multiplexers
Implementing Combinational Functions with Multiplexers

4. 3-1 Beginning Hierarchical Design
Combinational Circuits
A combinational logic circuit has:
A set of m Boolean inputs,
A set of n Boolean outputs, and
n switching functions, each mapping the 2m input combinations to an output such that the current output depends only on the current input values
A block diagram:
m Boolean Inputs
n Boolean Outputs
Combinatorial
Logic
Circuit

5. 3-1 Beginning Hierarchical Design
Design Procedure
Specification
Write a specification for the circuit if one is not already available
Formulation
Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification
Apply hierarchical design if appropriate
Optimization
Apply 2-level and multiple-level optimization
Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters

6. 3-1 Beginning Hierarchical Design
Design Procedure
Technology Mapping
Map the logic diagram or netlist to the implementation technology selected
Verification
Verify the correctness of the final design manually or using simulation

7. 3-1 Beginning Hierarchical Design
Design Example
Specification
4-Bit equality Comparator
Compares two binary vectors to determine whether they are equal or not
Inputs consist of tow vectors: A(3:0) and B(3:0)
Output is a single-bit variable E
A and B are equal then E=1
A and B are unequal then E=0

8. 3-1 Beginning Hierarchical Design
Design Example (continue)
Formulation

9. 3-1 Beginning Hierarchical Design
Design Example (continue)
3. Optimization
𝑁 𝑖 = 𝐴 𝑖 𝐵 𝑖 + 𝐴 𝑖 𝐵 𝑖
𝐸= 𝑁 0 + 𝑁 1 + 𝑁 2 + 𝑁 3

10. 3-1 Beginning Hierarchical Design
To control the complexity of the function mapping inputs to outputs:
Decompose the function into smaller pieces called blocks
Decompose each block’s function into smaller blocks, repeating as necessary until all blocks are small enough
Any block not decomposed is called a primitive block
The collection of all blocks including the decomposed ones is a hierarchy

11. 3-1 Beginning Hierarchical Design
Reusable Functions
Whenever possible, we try to decompose a complex design into common, reusable function blocks
These blocks are
verified and well-documented
placed in libraries for future use

12. 3-1 Beginning Hierarchical Design
Hierarchy

13. 3-1 Beginning Hierarchical Design
Top-Down versus Bottom-Up
A top-down design proceeds from an abstract, high-level specification to a more and more detailed design by decomposition and successive refinement
A bottom-up design starts with detailed primitive blocks and combines them into larger and more complex functional blocks
Design usually proceeds top-down to known building blocks ranging from complete CPUs to primitive logic gates or electronic components.
Much of the material in this chapter is devoted to learning about combinational blocks used in top-down design.

14. Technology Mapping Mapping Procedures 3-2 Technology Mapping
To NAND gates
To NOR gates
Mapping to multiple types of logic blocks in covered in the reading supplement: Advanced Technology Mapping.

15. Mapping to NAND gates 3-2 Technology Mapping Assumptions:
Gate loading and delay are ignored
Cell library contains an inverter and n-input NAND gates, n = 2, 3, …
An AND, OR, inverter schematic for the circuit is available
The mapping is accomplished by:
Replacing AND and OR symbols,
Pushing inverters through circuit fan-out points, and
Canceling inverter pairs

16. NAND Mapping Algorithm
3-2 Technology Mapping
NAND Mapping Algorithm
Replace ANDs and ORs:
Repeat the following pair of actions until there is at most one inverter between :
A circuit input or driving NAND gate output, and
The attached NAND gate inputs.

17. Ex. 3-2 Implementation with NAND gates
3-2 Technology Mapping
Ex. 3-2 Implementation with NAND gates
𝐹=𝐴𝐵+ (𝐴𝐵) 𝐶+ (𝐴𝐵) 𝐷 +𝐸

18. Mapping to NOR gates 3-2 Technology Mapping Assumptions:
Gate loading and delay are ignored
Cell library contains an inverter and n-input NOR gates, n = 2, 3, …
An AND, OR, inverter schematic for the circuit is available
The mapping is accomplished by:
Replacing AND and OR symbols,
Pushing inverters through circuit fan-out points, and
Canceling inverter pairs

19. NOR Mapping Algorithm Replace ANDs and ORs:
3-2 Technology Mapping
NOR Mapping Algorithm
Replace ANDs and ORs:
Repeat the following pair of actions until there is at most one inverter between :
A circuit input or driving NOR gate output, and
The attached NOR gate inputs.

20. Ex. 3-3 Implementation with NOR gates
3-2 Technology Mapping
Ex. 3-3 Implementation with NOR gates
𝐹=𝐴𝐵+ (𝐴𝐵) 𝐶+ (𝐴𝐵) 𝐷 +𝐸

21. 3-2 Technology Mapping
Verification
Verification - show that the final circuit designed implements the original specification
Simple specifications are:
truth tables
Boolean equations
HDL code
If the above result from formulation and are not the original specification, it is critical that the formulation process be flawless for the verification to be valid!

22. Basic Verification Methods
3-2 Technology Mapping
Basic Verification Methods
Manual Logic Analysis
Find the truth table or Boolean equations for the final circuit
Compare the final circuit truth table with the specified truth table, or
Show that the Boolean equations for the final circuit are equal to the specified Boolean equations
Simulation
Simulate the final circuit (or its netlist, possibly written as an HDL) and the specified truth table, equations, or HDL description using test input values that fully validate correctness.
The obvious test for a combinational circuit is application of all possible “care” input combinations from the specification

23. 3-3 Combinational Functional Blocks
Functions and Functional Blocks
The functions considered are those found to be very useful in design
Corresponding to each of the functions is a combinational circuit implementation called a functional block.
In the past, functional blocks were packaged as small- scale-integrated (SSI), medium-scale integrated (MSI), and large-scale-integrated (LSI) circuits.
Today, they are often simply implemented within a very- large-scale-integrated (VLSI) circuit.

24. 3-3 Combinational Functional Blocks
Block Diagram of a Sequential Circuit

25. 3-4 Rudimentary Logic Functions
Value-Fixing, Transferring, and Inverting
Functions of a single variable X
Can be used on the inputs to functional blocks to implement other than the block’s intended function

26. 3-4 Rudimentary Logic Functions
Multiple-Bit Function
Multi-bit Examples:
A wide line is used to represent a bus which is a vector signal
In (b) of the example, F = (F3, F2, F1, F0) is a bus.
The bus can be split into individual bits as shown in (b)
Sets of bits can be split from the bus as shown in (c) for bits 2 and 1 of F.
The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0 of F.

27. Homework Homework Read Text Chapter 4, pp. 213-301
Prepare Presentation
Problems