1. Logical Effort Basics
from Bart Zeydel

2. Logical Effort Components
Template
Template Width
Scaled by a
Input Capacitance increases by a · Ctemplate
Resistance decreases by Rtemplate / a
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

3. Logical Effort Input Capacitance
Cox  eox / tox (unit: F/m2)
Leff = L – 2xd
Cgate = CoxWLeff = CoxWL(1 – 2xd / L)
k1 = Cox(1 – 2xd / L)
Ctemplate(inv) = k1WnLn + k1WpLp
Cin(inv) = a · Ctemplate(inv)
Input Capacitance is the sum of the gate capacitances
Using LE, a denotes size in multiples of the template
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

4. Logical Effort Resistance
R = (r / t) (L / W) ohms
R = Rsheet (L / W) ohms
Rchannel = Rsheet (L / W) ohms
Rsheet = 1 / ( mCox ( Vgs – Vt )) ohms
m = surface mobility
k2 = Cox (Vgs – Vt)
Rchannel = L / (k2 m W) ohms
Rup(inv) = Rup-template(inv) / a
Rdown(inv) = Rdown-template(inv) / a
Resistance is dependent on channel width and process
Larger values of a result in lower resistance.
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

5. Logical Effort Parasitics
Cja junction capacitance per m2
Cjp periphery capacitance per m
W width of diffusion region m
Ldiff length of diffusion region m
Larger values of a result in increased parasitic cap,
however R decreases at same rate, thus constant RC delay.
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

6. RC Model for CMOS logic gate
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

7. LE Delay derivation for step input
Vout Id C
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

8. LE Model derivation (cont.)
Substituting in R and C to obtain k
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

9. Logical Effort Gate Delay Model
Gate Template
a Scaled Gate
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

10. Logical Effort Gate Delay Model
Simplify Analysis by Normalizing to Inverter Template
Doesn’t change
with a
Doesn’t change
with a
Same derivation can be performed for tr
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

11. Estimating g and p of Gates
Inverter
NAND2
NOR2 2 2 4 2 4 2 1 2 1 1
g = (2+1)/(2+1)
= 1
p = Cp-inv/Cinv = pinv
g = (2+2)/(2+1)
= 4/3
p = [(2+2+2)/(2+1)]pinv
= 2pinv
g = (4+1)/(2+1)
= 5/3
p = [(4+1+1)/(2+1)]pinv
= 2pinv
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

12. Prof. V. G. Oklobdzija: High-Performance System Design
130nm Delay of Gates vs. h
NOR2
NAND2
Inverter
Slope = t = 7.3ps
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

13. Normalized Delay of Gates vs. h
t = 7.3ps
NOR2: g=1.57, p=1.89
NAND2: g=1.14, p=1.45
Inverter: g=1, p=0.93
Effort Delay
Parasitic Delay
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

14. Normalized Delay Estimate of Gates vs. h
Note: To simplify analysis
Assume Cp-inv = Cinv
NOR2: g=5/3, p=2
NAND2: g=4/3, p=2
Inverter: g=1, p=1
Effort Delay
Parasitic Delay
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

15. Prof. V. G. Oklobdzija: High-Performance System Design
LE Path Delay
Gate 1
Gate 2
Gate 3
Cout
Input Capacitance Cin C2 C3
Logical Effort: g1 g2 g3
Parasitic Delay p1 p2 p3
Stage Effort: f1 f2 f3
Any n-stage path can be described using Logical Effort
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

16. LE Path Delay Optimization
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

17. LE Path Delay Optimization (cont.)
By Definition, Cin and Cout are fixed.
Solve for C2 and C3:
Minimum delay occurs when stage efforts are equal
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

18. Simplified Path Optimization
We want the effort of each stage to be equal.
= Path Effort
= Stage Effort
To quickly solve for F:
= Logical Effort
of the path
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

19. Delay Optimization Example
Cin = 1 C2 C3 C4 g
f = gh Ci
Gate 1 1
Gate 2 1
Gate 3 1
Gate 4 1 81
Total Delay = (84 + 4pinv)t
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

20. Delay Optimization Example
Cin = 1 C2 C3 C4 g
f = gh Ci
Gate 1 1
Gate 2 1
Gate 3 1
40.5
Gate 4 1 2
40.5
Total Delay = ( pinv)t
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

21. Delay Optimization Example
Cin = 1 C2 C3 C4 g
f = gh Ci
Gate 1 1
Gate 2 1
10.1
Gate 3 1 4
10.1
Gate 4 1 2
40.5
Total Delay = ( pinv)t
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

22. Delay Optimization Example
Cin = 1 C2 C3 C4 g
f = gh Ci
Gate 1 1
10.1
Gate 2 1
10.1
Gate 3 1 4
10.1
Gate 4 1 2
40.5
Total Delay = ( pinv)t
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

23. Optimal Sizing for Delay
Cin = 1 C2 C3 C4 g
f = gh Ci
Gate 1 1 3
Gate 2 1 3
Gate 3 1 3 9
Gate 4 1 3 27
Optimal Delay = (12 + 4pinv)t
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

24. Delay Optimization and Sizing Example
Cin = 1 C2 C3 C4
Use Logical Effort to optimize sizes for Delay
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

25. Prof. V. G. Oklobdzija: High-Performance System Design
Delay Optimization and Sizing Example
Cin = 1 C2 C3 C4
Size from output to input using fopt
Delay Estimate
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

26. Example 2: Path OptimizationC2 C4
Cin = 1 C3 g
f = gh Ci
Size
Gate 1 1
Gate 2
5/3
5/3*3/5 1
Gate 3
4/3
4/3*3/4 1
Gate 4 1 81
Total Delay = (85 + 6pinv)t
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

27. Example 2: Path Optimization
Cin = 1 C2 C3 C4 g
f = gh Ci
Size
Gate 1 1
3.66
Gate 2
5/3
3.66
2.2
Gate 3
4/3
3.66
8.06
6.04
Gate 4 1
3.66
22.1
Optimal Delay = ( pinv)t
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

28. Prof. V. G. Oklobdzija: High-Performance System Design
Example 2: LE Solution
Cin = 1 C2 C3 C4
Size from output to input using fopt
S1 = 1, S2 = 2.2, S3 = 6.04, S4 = 22.1
Delay Estimate
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

29. Logical Effort for Multi-path
From LE,
and
Minimum delay occurs when Da = Db or Fa = Fb (ignoring parasitics)
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

30. Logical Effort for Multi-path (cont.)
Branching:
Ratio of total capacitance to on-path capacitance
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

31. Logical Effort for Multi-path (cont)
Substituting C0 and C3
Since Minimum Delay occurs when Da = Db or Fa = Fb
Similarly
Branching = 2 when Ga = Gb and Cout1 = Cout2
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

32. Prof. V. G. Oklobdzija: High-Performance System Design
Example 3: Uniform Branching C6 C5
Cout2 = C5+C3
Cin = 1 C2 C4 C3 g
f = gh Ci b
Gate 1 1
Gate 2
5/3
10/3 1 2
Gate 3,5
4/3 1
Gate 4,6 1 81
Total Delay = ( pinv)t
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

33. Prof. V. G. Oklobdzija: High-Performance System Design
Example 3: Uniform Branching C6 C5
Cout2 = C5+C3
Cin = 1 C2 C4 C3 g
f = gh Ci b
Gate 1 1
4.36
Gate 2
5/3
4.36 2
Gate 3,5
4/3
4.36
5.69 1
Gate 4,6 1
4.36
18.6
Optimal Delay = ( pinv)t
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

34. Prof. V. G. Oklobdzija: High-Performance System Design
Example 3: LE Solution C6
Cout2 = C5+C3 C5
Cin = 1 C2 C3 C4
Size from output to input using fopt
Delay Estimate
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

35. Complex Multi-path Optimization
If each path has internal branching, ba and bb are as follows
Note: This solution and previous solution differ from that described in LE book (which is incorrect)
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design