1. Logical Effort Section 6.5-6.6.1

2. Problems: P6.2 Compute the oscillation frequency of a seven-stage ring oscillator using 0.18 micron technology. Does the size of the inverters make any difference in the result?

3. Problem P6.4 Determine the self-capacitance at the output assuming step changes at the inputs shown.

4. Sizing Issues

5. Proper Formulation of a Delay Problem

6. Reformulate a Delay Problem Key Concepts: Intrinsic Time Constant Fanout Ratio

7. Optimal Sizing of Inverter Chain

8. Stage Fanout

9. Delay Versus Fanout

10. Examples Examples 6.8 Examples 6.9

11. Series of Mixed Gates

12. Example Example 6.10

13. Derivation of Logic Effort

14. Obtain Logic Effort of a Gate From definition of intrinsic time constant

15. Determine LE by taking the ratio of Input Capacitances

16. Determine LE by taking the Delay Ratio

17. Determine the Parasitic Term 2 input-NAND 2 input-NOR Subtleties of Table 6.2

18. NAND2 NMOS in seriesPMOS in parallel

19. NAND3 NMOS in seriesPMOS in parallel

20. NAND4

21. NOR2