1. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 1 Logical Effort - sizing for speed

2. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 2 Sizing Logic Paths for Speed  Frequently, input capacitance of a logic path is constrained  Logic also has to drive some capacitance  Example: ALU load in an Intel’s microprocessor is 0.5pF  How do we size the ALU datapath to achieve maximum speed?  We have already solved this for the inverter chain – can we generalize it for any type of logic?

3. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 3 Buffer Example For given N: C i+1 /C i = C i /C i-1 find N: C i+1 /C i ~ 4 How to generalize this to any logic path? CLCL InOut 12N (in units of  inv )

4. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 4 Logical Effort p – intrinsic delay (3kR unit C unit  ) - gate parameter  f(W) g – logical effort (kR unit C unit ) – gate parameter  f(W) f – effective fanout (electrical effort) Normalize everything to an inverter: g inv =1, p inv = 1 Divide everything by  inv (everything is measured in unit delays  inv ) Assume  = 1.

5. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 5 Delay in a Logic Gate Gate delay : d = p + h effort delayintrinsic delay Effort delay : h = g f logical effort effective fanout = C out /C in Logical effort is a function of topology, independent of sizing. Electrical effort (effective fanout) is a function of load/gate size electrical effort =

6. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 6 Logical Effort (g)  Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates  Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current  Logical effort increases with the gate complexity

7. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 7 Logical Effort (g) Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 1 g = 4/3 g = 5/3

8. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 8 Logical Effort of Gates Fanout (f) Normalized delay (d) 1234567 g = 1 p = 1 d = 1+ f g = 4/3 p = 2 d = 2+ (4/3)f t pInv t pNAND Delay: d = p + g f effort delay, g f intrinsic delay, p

9. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 9 Add Branching Effort Branching effort:

10. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 10 Multistage Networks Stage effort: h i = g i f i Path electrical effort: F = C out /C in Path logical effort: G = g 1 g 2 …g N Branching effort: B = b 1 b 2 …b N Total path effort: H = GFB Path delay D =  d i =  p i +  h i

11. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 11 Optimum Effort per Stage Optimum delay is achieved when each stage bears the same effort: Minimum path delay Effective fanout of each stage: Stage efforts: g 1 f 1 = g 2 f 2 = … = g N f N

12. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 12 Optimal Number of Stages For a given load, and given input capacitance of the first gate, find optimum number of stages and optimal sizing Substitute ‘best stage effort’

13. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 13 Logical Effort From Sutherland, Sproul

14. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 14 Method of Logical Effort  Compute the path effort: H = GFB  Find the optimum number of stages: N ~ log 4 H  Compute the stage effort h = H 1/N  Sketch the path with this number of stages  Work either from either end, find sizes (gate capacitance): C in = C out   g i / h or C out = C in   h / g i Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999. C in C out h / g i = f i

15. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 15 Example: Optimize Path g 1 = 1 f 1 = a/1 g 2 = 5/3 f 2 = b/a g 3 = 5/3 f 3 = c/b g 4 = 1 f 4 = 5/c Compute path effort: F = f 1 f 2 f 3 f 4 = 5 G = g 1 g 2 g 3 g 4 = 25/9 H = GFB= 125/9 = 13.9 h = H 1/4 = 1.93 a,b,c mean capacitances f 1 = h/g 1 = 1.93 f 2 = h/g 2 = 1.16 f 3 = h/g 3 = 1.16 f 4 = h/g 4 = 1.93 Recall: h = const = f i g i Assume no branching: B=1 Compute gate sizes : a = 1.93 b = a h /g 2 = 2.23 c = b h /g 3 = 5g 4 /h = 2.59

16. EE141 © Digital Integrated Circuits 2nd Combinational Circuits 16 Example – 8-input AND