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SCIENTIFIC CMOS PIXELS
JIM JANESICK SARNOFF CORPORATION JULY 1, 2004
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ACKNOWLEDGEMENTS Jim Andrews Sarnoff Corporation
CN5300, 201 Washington Road Princeton, NJ Benjamin Muto, Mark Muzilla DRS TECHNOLOGIES Sensors & Targeting Systems 3330 Miraloma Ave. Anaheim, CA 92806
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■ CCD and CMOS imaging technologies will coexist.
CMOS vs CCD ■ CCD and CMOS imaging technologies will coexist. ■ CCD is a mature technology CMOS is currently not. ■ CMOS can compete with the CCD scientifically although major development is required. Ultimate performance is delivered by the pixel. ■ Hybrid sensors are combining technologies that can potentially deliver performance superior to CCD and CMOS bulk detectors.
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CCD IMAGERS Qualities Deficiencies
■ Text book performance for all parameters (QE, read noise, MTF, dark current, linearity, etc.). Deficiencies ■ Low high-energy radiation damage tolerance. e.g. proton bulk damage and resultant CTE degradation. ■ Significant off-chip electronic support required. ■ Difficulty with high-speed readout (inherently a serial read out device).
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CMOS IMAGERS Qualities Deficiencies
■ Very tolerant to high-energy radiation sources (long life time). ■ On- chip system integration (low power, low weight and compact designs). ■ High speed / low noise operation (inherently a parallel- random access readout device). Deficiencies ■ Currently lacks performance in most areas compared to the CCD (charge generation, charge collection, charge transfer and charge measurement).
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CMOS PIXELS
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SCIENTIFIC CMOS PIXEL CANDIDATES
3T PIXEL PINNED PHOTO DIODE DEEP N WELL PHOTO DIODE 5 T PIXEL CHARGE COUPLED PINNED PHOTO DIODE 6 T PIXEL BACKSIDE ILLUMINATED CHARGE COUPLED BURIED CHANNEL PHOTO GATE
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CRITICAL CMOS PERFORMANCE PARAMETERS
■ Quantum Efficiency (QE) ■ Modulation Transfer Function (MTF) ■ Read Noise (Source Follower and Reset Noise) ■ Full Well ■ Non Linearity ■ Charge Transfer Efficiency (CTE) ■ Dark Current ■ RAD Hardness
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QUANTUM EFFICIENCY PINNED PHOTO DIODE DELIVERS THE HIGHEST FRONTSIDE QE SENSITIVITY BACKSIDE ILLUMINATION DELIVERS THE HIGHEST QE POSSIBLE FOR ALL CMOS PIXEL ARCHITECTURES QE PINNING (100 % INTERNAL QE) HAS BEEN DEMONSTRATED BACKSIDE ACCUMULATION TECHNIQUES EMPLOYED: CHEMISORPTION UV CHARGING FLASH GATE ION IMPLANTATION MOLECULAR BEAM EPITAXIAL (MBE) NO FUNDAMENTAL BACKSIDE QE PROBLEMS HAVE BEEN IDENTIFIED
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QUANTUM EFFICIENCY
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BACKSIDE QE GOAL
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FULLY DEPLETED A CONDITION REQUIRED FOR LOW PIXEL CROSS AND HIGH MTF PERFORMANCE DIFFICULT TO ACHIEVE BECAUSE CMOS OPERATING VOLTAGES ARE LOW FULL DEPLETION TECHNIQUES: HIGH RESITIVITY SILICON DEEP N-WELL TECHNOLOGY THIN EPI SILICON SUBSTRATE BIAS DEEP BORON IMPLANT FULL DEPLETION HAS BEEN DEMONSTRATED FOR 10 um BACKSIDE ILLUMINATED CMOS ARRAYS HIGH RESISTIVITY SILICON MAY BE A FUNDAMENTAL PROBLEM BECAUSE OF CMOS SWITCH LATCH UP (EXCEPT FOR HYBRID ARRAYS) DEPLETION vs SIGNAL PROBLEM
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DEPLETION DEPTH vs SILICON RESISTIVITY
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DEPLETION vs SIGNAL PROBLEM
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DEPLETION vs SIGNAL PROBLEM
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READ NOISE vs READOUT MODES
3T PIXEL ROLLING SHUTTER READOUT LIMITED BY RESET NOISE (TRUE CDS CANNOT BE PERFORMED) 5T/6T CHARGE COUPLED PIXELS PROGRESSIVE SCAN READOUT LIMITED BY SOURCE FOLLOWER NOISE (TRUE CDS PROCESSING) SNAP READOUT LIMITED BY RESET NOISE (TRUE CDS CANNOT BE PERFORMED)
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SOURCE FOLLOWER READ NOISE
LIMITED BY FLICKER (1/f) RANDOM TELEGRAPH NOISE (RTS) PIXEL TO PIXEL NOISE VARIANCE (2 e- < noise < 15 e- pp) FLICKER NOISE DEPENDENT ON SOURCE FOLLOWER GEOMETRY AND DRAIN CURRENT WHITE NOISE IS NEGLIGIBLE
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PHOTO GATE PIXEL LOW LIGHT IMAGERY
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SOURCE FOLLOWER NOISE RANDOM TELEGRAPH NOISE (RTS)
RTS NOISE
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