1. ITRS Roadmap Design Process Open Discussion EDP 2001
Donald Cottrell
Si2, Inc.
November 22, /03/2000
EDP '2001

2. Technology Trend - The Big
Designer Productivity
Transistors per Month
Year
November 22, /03/2000
EDP '2001

3. Technology Trend - The Bad
% Mixed Signal %
Year
Diversity
November 22, /03/2000
EDP '2001

4. Technology Trend - The Ugly
Mutual Coupling
Noise
Coupled
External
Power
di/dt
IR Drops
Electromigration
High Frequency
Transmission lines
Reflections
November 22, /03/2000
EDP '2001

5. Breaking Down the “Walls”
Digital
Analog
Software
Architecture
RTL
Synthesis
FloorPlan
Layout
Checking
Mask Prep
Manufacture
November 22, /03/2000
EDP '2001

6. Breaking Down the “Walls”
Magma’s single unified data model enables a correct-by-construction design flow.
November 22, /03/2000
EDP '2001

7. EDA Evolution - 2001 1 2 3 ASCII MW Genesis ASCII
November 22, /03/2000
EDP '2001

8. Reality
No external vendor meets all IC design needs, All EDA vendors together don’t meet all needs.
Nearly impossible for startups to break into the business due to integration barriers,
Startups enter business with intent to be purchased, BUT once purchased by “big guys”, a time lag and loss of innovation result.
Industry partnerships provide value, BUT integration acts as a barrier.
November 22, /03/2000
EDP '2001

9. All or Nothing at All
November 22, /03/2000
EDP '2001

10. The Need - Customer Choice
FrameMaker
Access
Lotus123
CorelDraw
November 22, /03/2000
EDP '2001

11. Customize Solution to Fit the Need
Calibre SE
Mars-XTalk
Fire&Ice
November 22, /03/2000
EDP '2001

12. A Better Model 1 4 2 3 Open Model and API ASCII MW Genesis ASCII
November 22, /03/2000
EDP '2001

13. EDA System Needs Database
High Performance integration and tools: Architecture and Assembly Function, Performance, Power, RTL through Mask design and analysis
Constraint driven design tools (power, timing, signal integrity, …)
Integration via Open Architecture Industry-standard data model Industry-standard API
Incremental analysis and optimization
Concurrent design and analysis
Common Calculation Engines
Abstracted Model Builders Industry Standard interfaces
Architectural
Architectural
Design
Design
Calculation
Engines
Cell and
Core Library
Delay
Delay
Power
RTL
RTL
Extraction
Function
Design
Design
Properties
Cell Geometry
Synthesis
Synthesis
Abstract
Detailed
Process Lib
Floor Plan
Floor Plan
Substrate
Dielectric
Metal
Place&Route
Place&Route
Via
Incremental
Incremental
Industry Standard
Design API
Extraction
Extraction
Final
Final
Signoff
Signoff
Verification
Verification
Test
Generation
Database
November 22, /03/2000
EDP '2001

14. Standards vs. Innovation
Did SQL hurt Relational Database sales?
Did MAC grow faster than PC?
Are we happy with the rate of university research technology transfer?
Is there a better way to do cooperative design? SoC?
Can we continue with ASCII file exchange vs. true interoperability?
November 22, /03/2000
EDP '2001

15. Discussion Do we really need an Open Infrastructure?
Will an EDA MicroSoft emerge - Is that bad?
Can an EDA Linux model work?
Does one-size fit all?
Analog/RF/MEMS
ASIC (compiled HDL --> gates)
High-volume custom (uP, DSP, embedded memory, reprogrammable)
SOC (high integration, low cost, low TTM)
Memory
Are product markets significant?
Portable & Wireless, Broadband, Internet Switching, Mass Storage, Consumer, Computer, Automotive
Can we develop the necessary metrics?
ASIC
COTS P
Complexity
Return
November 22, /03/2000
EDP '2001

16. Market Drivers
November 22, /03/2000
EDP '2001

17. Market Drivers
November 22, /03/2000
EDP '2001

18. 1997 NTRS
November 22, /03/2000
EDP '2001

19. 1999 ITRS
November 22, /03/2000
EDP '2001