2. Sequential Circuits: Latches
Digital Systems
Section 9
Sequential Circuits: Latches

3. Need of Storage: Flight Attendant Call Button
Lecture
Digital Systems
Need of Storage: Flight Attendant Call Button
How can we implement a logic circuit for this?
Bit
Storage
Blue light
Call
button
Cancel
1. Call button pressed – light turns on Q
Call button
Cancel button
Bit
Storage
Blue light
Call
button
Cancel
2. Call button released – light stays on
OR Gate does not work. Q does not stay 1 when Call button returns to 0.
A form of feedback is needed in this circuit.
Bit
Storage
Blue light
Call
button
Cancel
3. Cancel button pressed – light turns off

4. Need of Storage: Control of Alarm System
Lecture
Digital Systems
Need of Storage: Control of Alarm System
For a certain alarm system, it is required that if someone moves through an infrared sensor (R), the alarm (A) will turn on and stays on until it is manually reset.
This circuit requires a memory element to keep the alarm on although sensor does not detect any movement anymore.
Memory
Element
Alarm
Buzzer
Infrared Sensor
Reset Button

5. Lecture
Digital Systems
Preview
At this stage, we realize that our circuits require memory to store intermediate data for further use.
So far, we only use combinational circuits. These cannot remember or store information / state after the inputs are removed.
In combinational circuit, the output depends only on the current inputs. For a given set of inputs, the output will always be the same.
Now, we will continue with sequential circuit. These circuits can store information / state from past inputs.
In sequential circuit, the output depends on the sequence of inputs (past and present). For a given set of inputs, the output might be different, depending on the stored information.
Sequential circuits use a signal (non-periodic enable/control signal or periodic clock signal) to determine when to store values.

6. Preview Sequential circuits need storage element: Latch and flip-flop
Lecture
Digital Systems
Preview
Sequential circuits need storage element:
Latch and flip-flop
Static Random Access Memory (SRAM)
Dynamic Random Access Memory (DRAM)
Latches and flip-flops are the basic elements for storing information. They are made of logic gates.
One latch or flip-flop can store one bit of information.
For latches, its input can affect the output as long as the enable signal is asserted (high).
For flip-flop, its input can affect the output only when the enable signal changes (falling edge or rising edge).
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

7. Combinational Circuit and Sequential Circuit
Lecture
Digital Systems
Combinational Circuit and Sequential Circuit
Combinational Circuit
Outputs
Inputs
Next state
Present state
Enable/ Control/ Clock
Sequential Circuit
Clock is a periodic external signal.
Clock synchronizes the state change, to occur at a certain time.
Clock

8. Lecture
Digital Systems
Sequential Circuit

9. Cross-coupled Inverters
Lecture
Digital Systems
Cross-coupled Inverters
As example of storage element, we can add feedback to a pair of inverters. This circuit has two stable states. It can be used to store one bit of information. 1 1 1
Feedback
Ring
Cross-coupled
In order to change the stored value, we can modify the cross-coupled inverter becomes a latch with set and reset:
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs. 1
 0
Set
 1
Set
Reset 1
 1
 1 1 1 1
 0
 1 1
 0

10. Basic S-R Latch (NANDs)
Lecture
Digital Systems
Basic S-R Latch (NANDs)
In S-R latch, S is used to set the element, making the output Q to one. R is used to reset or clear the element, setting the output Q to zero.
Characteristic table S R Q Q’ 1 S R
Qnext
Q’next X Q
S = 1, R = 1  hold the current output value
S = 0, R = 1  set the output value Q to 1
S = 1, R = 0  set the output value Q to 0
S = 0, R = 0  both outputs equal 1, invalid

11. Basic S-R Latch (NANDs)
Lecture
Digital Systems
Basic S-R Latch (NANDs)
The waveforms below are applied to the input of S-R latch (NANDs). Assume that initial Q = 0. Determine the Q waveform.

12. Basic S-R Latch (NANDs)
Lecture
Digital Systems
Basic S-R Latch (NANDs)
Normal resting state is S = 1 and R = 1.
At resting state, after the latch is reset, the state will be Q = 0 and Q’ = 1.
From the resting state, the output Q = 1 can be obtained by setting S momentarily to 0.
From the resting state, the output Q = 0 can be obtained by setting R momentarily to 0.

13. Application of Basic S-R Latch (NANDs)
Lecture
Digital Systems
Application of Basic S-R Latch (NANDs)
Avoiding Contact Bounce

14. Lecture
Digital Systems
IC of Basic S-R Latches

15. Basic S-R Latch (NORs) S-R latch can also be made from NOR Gates.
Lecture
Digital Systems
Basic S-R Latch (NORs)
S-R latch can also be made from NOR Gates. R S Q Q’
Characteristic table 1 S R
Qnext
Q’next X Q
S = 0, R = 0  hold the current output value
S = 0, R = 1  set the output value to 0
S = 1, R = 0  set the output value to 1
S = 1, R = 1  both outputs equal 0, invalid

16. Lecture
Digital Systems
Basic S-R Latch (NORs)
The waveforms below are applied to the input of S-R latch (NORs). Assume that initial Q = 0. Determine the Q waveform.

17. Basic S-R Latch (NORs) Normal resting state is S = 0 and R = 0.
Lecture
Digital Systems
Basic S-R Latch (NORs)
Normal resting state is S = 0 and R = 0.
At resting state, after the latch is set, the state will be Q = 1 and Q’ = 0.
From the resting state, the output Q = 1 can be obtained by setting S momentarily to 1.
From the resting state, the output Q = 0 can be obtained by setting R momentarily to 1.

18. Application of Basic S-R Latch (NORs)
Lecture
Digital Systems
Application of Basic S-R Latch (NORs)
Light Interruption Detection

19. Lecture
Digital Systems
Digital Pulses
In actual circuit, it takes time for a pulse waveform to change from one level to the other.
Characteristic measures are tr (rise time), tf (fall time), and tw (width/duration of the pulse).
Rise or fall time generally last less than one hundred nanosecond, and will be acceptable in most applications.

20. Timing Analysis: Logic-Gate Delay
Lecture
Digital Systems
Timing Analysis: Logic-Gate Delay
What happen at t10 ? (change from invalid state to no change).
S and R both go from invalid state S = R = 1 to S = R = 0.
If gate delays (td) are exactly the same  oscillation will occurs.
If gate delays are slightly different  one output with the faster gate will win the race  It can be Qa = 1, Qb = 0 or Qa = 0, Qb = 1  the final state will be unpredictable.

21. Lecture
Digital Systems
Gated Latches
A gated latch is a basic latch that includes an input gating and a control signal.
A gated latch retains its existing state when the control signal is equal to 0. Its state may be changed when the control signal is equal to 1.
This control signal can also be a clock signal.
We consider two types of gated latches:
Gated S-R latch: uses inputs S and R to set the output to 1 or reset it to 0, respectively.
Gated D latch: uses input D to set the output to a state that has the same logic value as the input D.

22. Gated S-R Latch (NANDs)
Lecture
Digital Systems
Gated S-R Latch (NANDs)
In this gated S-R latch, a control signal C is added.
When C = 0, output change is disabled.
When C = 1, output change is enabled.
Characteristic table

23. Gated S-R Latch (NORs) Characteristic table Timing diagram
Lecture
Digital Systems
Gated S-R Latch (NORs)
Characteristic table
Timing diagram
To get better control of the state changes, we must limit when the input signals affect the outputs.
In gated latch, the states will only change when the control signal is high.
When the control signal goes low, the last output will be held.

24. Gated D Latch Gated D latch has two inputs: D (data) and C (control).
Lecture
Digital Systems
Gated D Latch
Gated D latch has two inputs: D (data) and C (control). S R Q Q’ C D
When C = 1  S = D’, R = D  Q = D.
The output is set to the value of D.
When C = 0  S = R = 1  Q is hold
The latch holds previous value.
Characteristic table 1 X D C
Qnext
Q’next Q

25. Timing diagram of Gated D Latch
Lecture
Digital Systems
Gated D Latch
Timing diagram of Gated D Latch
The output Q will only change and track the input D when the control signal is high
When the control signal goes low, the last output will be held

26. Exercise: Gated D Latch
Lecture
Digital Systems
Exercise: Gated D Latch
Determine the characteristic table of the following gated D latch. How to set the control signal C so that we can write the data D to the output Q? S R Q Q’ C D C D
Qnext
Q’next Q S R

27. Lecture
Digital Systems
Summary of Latches
Latches are based on combinational gates (NAND, NOR, NOT).
A latch is made of 2 NANDs or 2 NORs, and is used to store 1 bit of information.
Latches store data even after data input has been removed.
S-R latches operate similar to cross-coupled inverters with control inputs (S for set and R for reset).
With additional gates, an S-R latch can be converted to a D latch (D stands for Data).
D latch is simple to understand conceptually, as a circuit to store one bit of data.
When C = 1, data input D is stored and given as output Q.
When C = 0, data input D is ignored and previous output value is held at Q.

28. Disadvantages of Transparent Latches
Lecture
Digital Systems
Disadvantages of Transparent Latches D C Q Q’
In a series of D latches, when C = 1, then
D will be passed through the entire circuit
Any hazards / glitches of D will pass through the entire circuit
It is better to control that D should be passed only at a certain event, when C changes value from 0 to 1 (rising edge) or from 1 to 0 (falling edge)  we have a Flip-Flop.
We will discuss flip-flops in the next meeting.

29. Atanua: Real-Time Logic Simulator
Lecture
Digital Systems
Atanua: Real-Time Logic Simulator
Download Atanua from
Play around with this application. There will be assignments that require this software.

30. X X X X X X X November Schedule IT-2 W8 (14:30) W9 (14:30) W10 (07:30)
Lecture
Digital Systems
November Schedule IT-2
W8 (14:30)
W9 (14:30)
W10 (07:30) X X X X X X X
W11 (14:30)
 Quiz 2
W12 (14:30)

31. X X X X X X X November Schedule IT-1 W8 (07:30) W9 (07:30) W10 (14:30)
Lecture
Digital Systems
November Schedule IT-1
W8 (07:30)
W9 (07:30)
W10 (14:30) X X X X X X X
W11 (07:30)
 Quiz 2
W12 (07:30)

32. Lecture
Digital Systems
Homework 7 (1/2)
Bit
Storage
Blue light
Call
button
Cancel
Circuit?
Now, show how can an R-S latch with NAND implementation can be used to solve the Flight Attendant Call Button Problem. Draw the complete circuit.
Complete the timing diagram of a gated D latch, if the control (C) and the input data (D) is given as below. The initial value for Q and Q’ are as indicated.
See next slide.

33. Lecture
Digital Systems
Homework 7 (2/2)
For the S-R latch with NOR implementation (see below), the initial value for the output is Q = 0, Q’ = 1.
Draw the output Q and Q’ for the input signals S and R as given below, for the case of: (i) td1 >> td2 (ii) td1 << td2
Hint: Time delay td will be crucial in the occurrence of invalid state. R S Q Q’
td1
td2
Please write your Class number after your Student ID.
Deadline: 1 day before class.
Monday, 6 November 2017 (Class 2).
Tuesday, 7 November 2017 (Class 1).