1. VBSS Voice over IP Bandwidth Saving System Prototype Demonstration
Cheri Perception
VBSS Voice over IP Bandwidth Saving System Prototype Demonstration

2. Company Profile Hubert Pan Cathy Zhang Bryan Cua Tilson Chung
Bryan Cua (CEO) - responsible to oversee the entire project and to maintain team organization
Tilson Chung (CTO) - responsible for project specifications and development of the project
Hubert Pan (COO) - in charge of the entire operation in regards to the project
Cathy Zhang (CFO) - responsible for all financial concerns, such as managing the budget and resolving financial issues

3. Overview Product Overview Operation Simulation Statistics Prototype
Future Development

4. VBSS
Product Overview

5. Product Concept VBSS Voice over IP Bandwidth Saving System
Product as Dynamic Operator
Paper Cup Analogy
Hypothetical situation: phone line
Only one conversation can go through this line.
Our product will enable two conversations to go through this line at the same time
Hypothetical metaphor: pipe
-Put a solution through the pipe
-At the other end, the individual components will be separated

6. Motivation Reduce operation costs Minimize network resource usage
Pioneer dual voice
stream compression

7. Comparison Single stream compression Dual stream compression
Existing Technology
Vbss product
Single stream compression
Dual stream compression
Designed on top of single stream compression

8. VBSS
Operation

9. System Diagram
John
Jill
Alex
Alice

10. System Diagram
John
Jill
Big Pipe (Internet)
Alex
Alice

11. System Diagram
John
Jill
Big Pipe (Internet)
Alex
Alice

12. Speech Characteristics
Voiced
Unvoiced
Silent
We decided to use MicroBlaze processor as opposed to the original proposed PowerPC405 processor.

13. VBSS
Simulation

14. Software Simulation MATLAB, C++ Pulse Code Modulation Voice recorded
Webcam Microphone
We decided to use MicroBlaze processor as opposed to the original proposed PowerPC405 processor.

15. Algorithm Parts Formant Estimation Fundamental Frequency Estimation
Linear and nonlinear filters
We decided to use MicroBlaze processor as opposed to the original proposed PowerPC405 processor.

16. Matlab Result Before After
We decided to use MicroBlaze processor as opposed to the original proposed PowerPC405 processor.

17. VBSS
Prototype

18. Prototype Components A small network support up to 6 devices
4 Grandstream
VoIP phones PC
FPGA board (Xilinx XUP-V2P)
We decided to use MicroBlaze processor as opposed to the original proposed PowerPC405 processor because powerpc doesn’t support FSL. 32-bit MicroBlaze v4.00a
Low-Frequency On-Chip Peripheral Bus (OPB)
Fast Simplex Link Bus (FSL)
Fast Fourier Transform
G711 μ-law codec

19. Xilinx XUP-V2P Hardware (Xilinx XUP-V2P): 32-bit MicroBlaze processor
Low-Frequency On-Chip Peripheral Bus (OPB)
Fast Simplex Link Bus (FSL)
Fast Fourier Transform
G711 μ-law codec
32-bit MicroBlaze v4.00a
Low-Frequency On-Chip Peripheral Bus (OPB) 100MHz
Fast Simplex Link Bus (FSL) 5V-oneway conneciton, we have implemented the 1024 FFT and a codec block that’s able to encode and decode between PCM voices and G711 encoded data on the FSL bus,
Fast Fourier Transform-hardware based
G711 μ-law codec

20. Hardware Architecture
Here is the system diagram for our hardware architecture.
Our hardware architecture features a single 32bits MicroBlaze V4.00a processor clocked at 100MHz, a high frequency Processor Local Bus (PLB), and a low‐frequency On‐chip Peripheral Bus (OPB).
LocalMemory Bus (LMB)
Fast Simplex Link (FSL) - The FSL channels are dedicated unidirectional point-to-point data streaming interfaces
Universal Asynchronous Receiver/Transmitter (UART)
performs parallel to serial conversion on characters received from the CPU and serial to parallel conversion on characters received from a modem or microprocessor peripheral
A BRAM memory subsystem consists of the controller along with the actual BRAM components that are included in the bram_block peripheral.

21. VBSS
Statistics

22. Conventions
Frames
Packet

23. Network Resource Usage
Packet (pkt) Size
= 218 bytes/pkt = 1744 bits/pkt
Data Packets arrive every 20 ms (λi = 1 for each phone)
λT = = = 200 pkt/s
= bits/s
G711 Voice packet consist of 160bytes of data, and in our system, we have 58byte of overhead

24. Network Resource (cont)
Processing Time Line for One Phone
Packet Processing
Time Division
20 ms
μT ≈ for 2 pkt
Again, there are four phones and therefore we have a total of 8 packets within approximately every 40 ms
C = Packet Service Rate × Average Packet Length
= (260.4 packets/s) × (1744 bits/packet)
= Mbps

25. Network Resource (conc)
10/100 Mbps switch accommodates the system capacity
System Utilization = Mbps ÷ 10 Mbps = 4.54%
Traffic Intensity = ρ = λT ÷ μT ≈ 76.8 %
ρ = λT ÷ μT ≤ 1 means utilization is maximized while the buffer will not overload over time.

26. Prototype Result Speech Characteristic Type of Frame % of Frames
Combined
~ 60%
Overall Saving
~ 30%
Voiced
~ 90%
Unvoiced
~ 10%
Module-added Delay
We decided to use MicroBlaze processor as opposed to the original proposed PowerPC405 processor.
Module
Time
Autocorrelation
0.432ms
PEF
0.654 ms
Send Packet Function
0.0425ms
MLP
0.214ms

27. VBSS
Future Development

28. Theory and Reality Simulation vs Prototype
No packets
Clear-cut frames
Calculation Precision
Prototype Environment too different from reality
Single network port board
Lone product
Low interference
Differences between the real system and our prototype

29. Algorithm Improvement
Robustness
Problems
Thresholds
Background noise
Noise between frames
Differences between the real system and our prototype

30. Hardware Restriction Processing power Network Interfaces
Differences between the real system and our prototype

31. Acknowledgement
Professors
Lakshman One
Steve Whitmore
Lesley Shannon

32. Questions ?