1. Lecture 10 Sequential Circuit ATPG Time-Frame Expansion
Problem of sequential circuit ATPG
Time-frame expansion
Nine-valued logic
ATPG implementation and drivability
Complexity of ATPG
Cycle-free and cyclic circuits
Summary
Original slides copyright by Mike Bushnell and Vishwani Agrawal

2. Sequential Circuits
A sequential circuit has memory in addition to combinational logic.
Test for a fault in a sequential circuit is a sequence of vectors, which
Initializes the circuit to a known state
Activates the fault, and
Propagates the fault effect to a primary output
Methods of sequential circuit ATPG
Time-frame expansion methods
Simulation-based methods

3. Example: A Serial AdderAn Bn 1 1
s-a-0 D X 1 1 D X Cn
Cn+1 X 1
Combinational logic Sn X FF

4. Time-Frame Expansion Time-frame -1 Time-frame 0 An-1 Bn-1 An Bn Cn-1
s-a-0 D X
s-a-0 D D 1 1
Cn-1 1 D X Cn 1 D 1
Cn+1 X 1
Combinational logic
Combinational logic 1
Sn-1 Sn X D FF

5. Concept of Time-Frames
If the test sequence for a single stuck-at fault contains n vectors,
Replicate combinational logic block n times
Cut at flip-flops
Place fault in each block
Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic
Vector -n+1
Vector -1
Vector 0
Fault
Unknown
or given
Init. state
State
variables
Next
state
Time-
frame
-n+1
Time-
frame -1
Time-
frame
Comb.
block
PO -n+1
PO -1
PO 0

6. Example
FF1 B A
FF2
s-a-1

7. Five-Valued Logic (Roth) 0,1, D, D, XA
s-a-1
s-a-1 D D X X X
FF1
FF1 X D D
FF2
FF2 B X B X
Time-frame -1
Time-frame 0

8. Nine-Valued Logic (Muth) 0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, XA X
s-a-1
s-a-1
0/1
X/1 X
0/X
0/X
FF1
FF1 X
0/1
X/1
FF2
FF2 B X B
0/1
Time-frame -1
Time-frame 0

9. Implementation of ATPG
Select a PO for fault detection based on drivability analysis.
Place a logic value, 1/0 or 0/1, depending on fault type and number of inversions.
Justify the output value from PIs, considering all necessary paths and adding backward time-frames.
If justification is impossible, then use drivability to select another PO and repeat justification.
If the procedure fails for all reachable POs, then the fault is untestable.
If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can be justified, then the fault is potentially detectable.

10. Drivability Example
(11, 16)
(10, 15)
(22, 17)
(10, 16)
d(0/1) =
d(1/0) = 32 8
s-a-1
d(0/1) = 4
d(1/0) =
d(0/1) =
d(1/0) = 20 8 8
(5, 9)
(4, 4)
(17, 11)
d(0/1) = 9
d(1/0) =
(CC0, CC1)
= (6, 4)
(6, 10)
d(0/1) = 120
d(1/0) = 27 8 FF
d(0/1) = 109
d(1/0) =
We assign a large value, here 100, for propagating through a FF. The goal is to make the cost of going through the FF high enough that a combinational path, or one with fewer clock cycles, is preferred. But note that the combinational controllability here only treats the FF as a cost of 1 (e.g. a buffer), rather than sequential controllability. This is used in choosing a path in the next time frame. This is not accurate, since in the next time frame additional input values may be required, rather than keeping the PIs the same. 8
CC0 and CC1 are SCOAP combinational controllabilities
d(0/1) and d(1/0) of a line are effort measures for driving
a specific fault effect to that line

11. max = Number of distinct vectors with 9-valued elements = 9Nff
Complexity of ATPG
Synchronous circuit -- All flip-flops controlled by clocks; PI and PO synchronized with clock:
Cycle-free circuit – No feedback among flip-flops: Test generation for a fault needs no more than dseq + 1 time-frames, where dseq is the sequential depth.
Cyclic circuit – Contains feedback among flip-flops: May need 9Nff time-frames, where Nff is the number of flip-flops.
Asynchronous circuit – Higher complexity!
Smax
Time-
Frame
max-1
Time-
Frame
max-2 S3
Time-
Frame -2 S2
Time-
Frame -1 S1
Time-
Frame S0
max = Number of distinct vectors with 9-valued elements = 9Nff

12. Cycle-Free Circuits
Characterized by absence of cycles among flip-flops and a sequential depth, dseq
dseq is the maximum number of flip-flops on any path between PI and PO
Both good and faulty circuits are initializable
Test sequence length for a fault is bounded by dseq + 1

13. All faults are testable. See Example 8.6.
Cycle-Free Example
Circuit F2 2 F3 F1 3
Level = 1 F1 F2 F3
Level = 1 2 3
s - graph
dseq = 3
All faults are testable. See Example 8.6.

14. Cyclic Circuit Example
Modulo-3 counter Z
CNT F2 F1
s - graph F1 F2

15. Modulo-3 Counter Cyclic structure – Sequential depth is undefined.
Circuit is not initializable. No tests can be generated for any stuck-at fault.
After expanding the circuit to 9Nff = 81, or fewer, time-frames ATPG program calls any given target fault untestable.
Circuit can only be functionally tested by multiple observations.
Functional tests, when simulated, give no fault coverage.

16. Adding Initializing Hardware
Initializable modulo-3 counter Z
CNT F2 F1
s-a-0
s-a-1
CLR
s-a-1
s-a-1
Untestable fault
Potentially detectable fault
s - graph F1 F2

17. Benchmark Circuits Circuit PI PO FF Gates Structure Seq. depth
Total faults
Detected faults
Potentially detected faults
Untestable faults
Abandoned faults
Fault coverage (%)
Fault efficiency (%)
Max. sequence length
Total test vectors
Gentest CPU s (Sparc 2)
s1196 14 18
529
Cycle-free 4
1242
1239 3
99.8
100.0
313 10
s1238 14 18
508
Cycle-free 4
1355
1283 72
94.7
100.0 3
308 15
s1488 8 19 6
653
Cyclic --
1486
1384 2 26 76
93.1
94.8 24
525
19941
s1494 8 19 6
647
Cyclic --
1506
1379 2 30 97
91.6
93.4 28
559
19183

18. Issues Circuits with high sequential depth are very difficult to test
Pipelined (type of cycle-free) circuits are sequential, but essentially look combinational, just with clock cycles of input-output delay
- Can use combinational ATPG
Circuits with no reset state are difficult to test
- Must run circuit to get to known state
- Worse if cyclic circuit

19. Summary Combinational ATPG algorithms are extended:
Time-frame expansion unrolls time as combinational array
Nine-valued logic system
Justification via backward time
Cycle-free circuits:
Require at most dseq time-frames
Always initializable
Cyclic circuits:
May need 9Nff time-frames
Circuit must be initializable
Full or partial scan can make circuit cycle-free

20. Practical Testing Only small sequential circuits can be tested
- Fault coverage often low
- ATPG time too high
Use mostly-full scan to minimize number of unscanned flip-flops
Initialize most unscanned flip-flops
Main source of X values are “blackbox” memories
- “Blackbox” means ATPG does not see inside module
- Cannot make these X’s go away