1. CS775: Computer Architecture
Lecture 1: Introduction and Review of Technology Trends

2. What is Computer Architecture?
Functional operation of the individual HW units within a computer system, and the flow of information and control among them.
Programming
Parallelism
Technology
Language
Interface
Computer Architecture:
Interface Design
(ISA)
Hardware Organization OS
Applications
Measurement & Evaluation

3. Course Objectives
To evaluate the issues involved in choosing and designing instruction set.
To learn concepts behind advanced pipelining techniques.
To understand the “hitting the memory wall” problem and the current state-of-art in memory system design.
To understand the qualitative and quantitative tradeoffs in the design of modern computer systems

4. Computer Architecture Topics
Input/Output and Storage
Disks, WORM, Tape
RAID
Emerging Technologies
Interleaving Memories
DRAM
Coherence,
Bandwidth,
Latency
Memory
Hierarchy
L2 Cache
L1 Cache
Addressing,
Protection,
Exception Handling
VLSI
Instruction Set Architecture
Pipelining, Hazard Resolution,
Superscalar, Reordering,
Prediction, Speculation,
Vector, DSP
Pipelining and Instruction
Level Parallelism

5. Computer Architecture Topics
Shared Memory,
Message Passing,
Data Parallelism P M P M P M P M
° ° °
Network Interfaces S
Interconnection Network
Processor-Memory-Switch
Topologies,
Routing,
Bandwidth,
Latency,
Reliability
Multiprocessors
Networks and Interconnections

6. Measurement and Evaluation
Architecture is an iterative process:
Searching the space of possible designs
At all levels of computer systems
Creativity
Cost /
Performance
Analysis
Good Ideas
Mediocre Ideas
Bad Ideas

7. Issues for a Computer Designer
Functional Requirements Analysis (Target)
Scientific Computing – HiPerf floating pt.
Business – transactional support/decimal arith.
General Purpose –balanced performance for a range of tasks
Level of software compatibility
PL level
Flexible, Need new compiler, portability an issue
Binary level (x86 architecture)
Little flexibility, Portability requirements minimal
OS requirements
Address space issues, memory management, protection
Conformance to Standards
Languages, OS, Networks, I/O, IEEE floating pt.

8. Computer Systems: Technology Trends
1988
Supercomputers
Massively Parallel Processors
Mini-supercomputers
Minicomputers
Workstations
PC’s
2002
Powerful PC’s and SMP Workstations
Network of SMP Workstations
Mainframes
Supercomputers
Embedded Computers

9. Why Such Change in 10 years?
Performance
Technology Advances
CMOS (complementary metal oxide semiconductor) VLSI dominates older technologies like TTL (transistor transistor logic) in cost AND performance
Computer architecture advances improves low-end
RISC, pipelining, superscalar, RAID, …
Price: Lower costs due to …
Simpler development
CMOS VLSI: smaller systems, fewer components
Higher volumes
Lower margins by class of computer, due to fewer services
Function :Rise of networking/local interconnection technology

10. Processor Performance Trends
1000
Supercomputers
100
Mainframes 10
Minicomputers 1
Microprocessors
0.1
1965
1970
1975
1980
1985
1990
1995
2000
Year

11. Technology Trends: Microprocessor Capacity
“Graduation Window”
Alpha 21264: 15 million
Pentium Pro: 5.5 million
PowerPC 620: 6.9 million
Alpha 21164: 9.3 million
Sparc Ultra: 5.2 million
Moore’s Law
CMOS improvements:
Die size: 2X every 3 yrs

12. Memory Capacity (Single Chip DRAM)
year size(Mb) cyc time ns ns ns ns ns ns ns

13. Updated Technology Trends (Summary)
Capacity Speed (latency)
Logic x in 4 years 2x in 3 years
DRAM 4x in 3 years 2x in 10 years
Disk 4x in 2 years 2x in 10 years
Network (bandwidth) 10x in 5 years

14. Processor Performance (1.35X before, 1.55X now)
1.54X/yr

15. Performance Trends (Summary)
Workstation performance (measured in Spec Marks) improves roughly 50% per year (2X every 18 months)
Improvement in cost performance estimated at 70% per year

16. A Question to Ponder On
In the CISC vs. RISC debate a key argument of the RISC movement was that because of its simplicity, RISC would always remain ahead.
If there were enough transistors to implement a CISC on chip, then those same transistors could implement a pipelined RISC
If there was enough to allow for a pipelined CISC there would be enough to have an on-chip cache for RISC. And so on.
After 20 years of this debate what do you think?
Hint: Think of commercial PC’s, Moore’s law and some of the data in the first chapter of the book (and on these slides)