1. Digital Logic Design Sequential Circuits (Chapter 6)
Instructor: Oluwayomi Adamo

2. Combinational vs. Sequential
Combinational circuit:
Output is a function of input
No memory
Example: ?
Sequential circuit:
Output is a function of input and something else stored in the circuit
Internal memory

3. Parallel and Serial Adders1
Four-bit
Adder S C
One-bit
Adder 1
time
time
One-bit
memory
Memory initialized to 0 (initial carry = 0)
Time synchronization of Inputs, output, memory (clock)

4. Another Example of Sequential Circuit
Four-year degree program:
Student can be in four states (Fr, So, Jr, Sr)
One-bit yearly input, 1 (pass) or 0 (fail)
Output = 1 (degree completed), 0 (in progress)
State diagram:
0/0
0/0
0/0
0/0 Fr
1/0 So
1/0 Jr
1/0 Sr
Initial state
1/1

5. State Table or Excitation Table
Input
Present State
Next State
Output Fr So Jr Sr 1
Initial State: Fr

6. State Table (Alternative Form)
Next state/output
Inputs
0 1
Fr/0
So/0
Jr/0
Sr/0
Sr/1 Fr So Jr Sr
Present state

7. When Is Circuit Not Combinational?
When the input does not completely control output.
For a logic circuit without feedback, input uniquely determines the output.
Examples of non-combinational (sequential) circuits:
Toggling 0-1
0 or 1
1 or 0
Odd inversions
Even inversions

8. SR Latch: Basic Sequential Circuit
Feedback loop with even number of inversions (no oscillation?).
Output(s): two sets of logic values from the loop.
Inputs:
Control loop logic values
Set the loop in “store” state

9. Adding Inputs to Feedback LoopR Q Q

10. NOR Set-Reset (SR) LatchQ Q S R Q Q Q Q S R
Symbol used in Logic schematics
Also drawn as

11. States of Latch State S R Q Q Set 1 Reset Store Prev. Q Prev. Q
Reset
Store
Prev. Q
Prev. Q
Illegal

12. The “Set” State Loop is broken Behavior is combinational. S = 1 Q = 1

13. The “Reset” State Loop is broken Behavior is combinational. S = 0
Q = 0
Q = 1
Loop is broken
Behavior is combinational.

14. The “Store” State Loop is activated; behavior is sequential. S = 0

15. The “Illegal” State
S = 1
R = 1
Q = 0
Q = 0
Loop is broken in two places and inconsistent values inserted.

16. “Illegal” State Cannot Be Stored
Assume two gates have equal delays.
S = 1 → 0
R = 1 → 0
Q = 0 → 1 → 0 → 1 → . . .
Q = 0 → 1 → 0 → 1 → . . .
Output oscillates with a period of loop delay. For unequal gate
delays, faster gate will settle to 1 and slower gate to 0. This is
known as RACE CONDITION.

17. Excitation Table of SR Latch
Excitation inputs
Present state
Next state
Name of State S R Q Q*
Store 1
Reset
Set
Illegal
Race condition

18. Characteristic Equation for SR Latch
Next-state function:
Treat illegal states as don’t care
Minimize using Karnaugh map
Characteristic equation, Q* = S +RQ S  1 Q R

19. State Diagram of SR Latch
SR = 0X
SR = X0
Q = 0
Q = 1
SR = 01

20. Clocked SR Latch S CK R
SR-latch Q Q

21. Delay Latch or D-Latch D CK Q Q

22. Setup and Hold Times of Latch
Signals are synchronized with respect to clock (CK).
Operation is level-sensitive:
CK = 1 allows data (D) to pass through
CK = 0 holds the value of Q, ignores data (D)
Setup time is the interval before the clock transition during which data (D) should be stable (not change). This will avoid any possible race condition.
Hold time is the interval after the clock transition during which data should not change. This will avoid data from latching incorrectly.

23. Latch Inputs tp 1 D
time ts th 1 CK
time tr

24. JK-Latch SR-latch Characteristic Equation, Q = JQ* + K Q*
Where Q = present state, Q* = previous state

25. T-Latch (Toggle Latch)
SR-latch J K Q Q T
Characteristic Equation, Q = TQ* + T Q*
Where Q = present state, Q* = previous state

26. Master-Slave D-Flip-Flop
Master latch
Slave latch D CK Q Q

27. Master-Slave D-Flip-Flop
Uses two level-sensitive clocked D-latches.
Transfers data (D) with one clock period delay.
Operation is edge-triggered:
Negative edge-triggered, CK = 1→0, Q = D (previous slide)
Positive edge-triggered, CK = 0→1, Q = D

28. Negative-Edge Triggered D-Flip-Flop
Clock period, T
Master open
Slave closed
Slave open
Master closed CK D
Triggering clock edge
Hold time
Setup time
Data
stable
Data can change
Data can change
Time

29. D-Flip-Flop With CLEAR
CLR
Master latch
Slave latch D CK Q Q

30. D-Flip-Flop With PRESET
Master latch
Slave latch D CK Q Q
PRESET

31. Symbols for Latch and D-Flip-FlopsCK D
Q (LATCH)
Level sensitive
Q (DFF)
Pos. Edge Triggered
Neg. Edge Triggered Q D CK D CK Q D CK Q

32. Register (3-Bit Example)
Stores parallel data
Parallel input
D D D2
CLR CK
CLR
D Q CK
CLR
D Q CK
CLR
D Q CK
Q Q Q2
Parallel output

33. Shift Register (3-Bit Example)
Stores serial data (parallel output)
Delays data (serial output)
CLR D
Serial
input CK
Serial
output
CLR
D Q CK
CLR
D Q CK
CLR
D Q CK
Q Q Q2
Parallel output