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Computer Architectures M

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Presentation on theme: "Computer Architectures M"— Presentation transcript:

1 Computer Architectures M
Memory Systems Computer Architectures M

2 Frequencies vs. periods
1 Hz 1000 msec 1sec ?? 40 msec 1 KHz 1000 microsec 1 msec 40 KHz 25 microsec 1 MHz 1000 nsec 1 microsec 250 MHz 4 nsec 1 GHz 1000 Psec 1 nsec 3 GHz ?? 60 GHz 16,6 psec 1 THz 1 psec 25 Hz 330 psec

3 EPROM memories EPROM CE* OE* 128K  8 Cell M/bit i Di
Non volatile read-only memories 1 VPP VCC 32 Capacities: two’s multiples: 32K, 64K, 128K, 256K…… PGM* 2 A16 31 NC 3 A15 30 Access time: ns A14 4 A12 29 A7 A13 5 28 Ai CE* OE* Di Tce Tacc Toe A6 A8 6 27 A5 A9 7 26 A11 8 A4 25 OE* 9 A3 24 A2 A10 10 23 11 A1 CE* 22 12 A0 D7 21 D6 13 D0 20 14 D1 D5 19 D4 15 D2 18 CE* OE* Di Cell M/bit i Tri-state driver GND D3 16 17 128K  8

4 Read Cycle Write Cycle RAM memories(SRAM) RAM 128K  8 Ai CE* Tce Toe
NC VCC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Ai CE* OE* I/Oi Tce Tacc Toe (Out) Read Cycle 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A16 A15 A14 NC A12 WE* A7 A13 A6 A8 A5 A9 A4 A11 A3 OE* A2 A10 A1 CE* Ai CE* WE* I/Oi Taw Twp (In) Tds Write Cycle A0 I/O7 I/O0 I/O6 I/O1 I/O5 I/O2 I/O4 GND I/O3 128K  8 Volatiles memories, readable and writable Capacity four’s multiples: 8K, 32K, 128K, 512K…… Access time: 5-40 ns DRAM: 1 transistor per bit, higher capacity, less speed

5 2n  N => 2n cells each of N bits
WR RD Data bit RAM cell D E C O R 2n  N => 2n cells each of N bits Tri-state driver j C Qi D Cell Address: “j”

6 Decoder and Decoder matrix
C D “column decode” (AND => associative property) A B “row decode”

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12 Register File (1 read-port, 1 write-port)
C O R 1 M-1 EN* n Read_Address Write_Address RD* WR* N Write_Data Read_Data CK D[0..N-1] WE* OE* O[0..N-1] R0 R1 RM-1 N.B. : M=2n A memory device is a register file

13 Memories with 2K bytes Any memory (and in particular memories with 8-bit parallelism – the only we will address), with 2k cells, has internally a k-variables decoder with E enable (negative true) input (this means that when E = 1 none of the outputs of the decoder is active) which selects one of the memory bytes. The memory interface has therefore the following signals Address bits ( An….A0) which select the addressed byte (if E enabled) Data bits (D7….D0) At least one chip select (CS*) (called also “chip enable” (CE* - asterisk means «negative true») which is the enable of the decoder. If CS* is inactive (=1) it means that no byte of this memory (of this «chip») is addressed. CS* is used to selected a memory device when multiple devices are present A memory bank (device) is «aligned» if its lowest address within the entire memory system is located at an address multiple of 2k (a 4 cells device is aligned if its two LSBs address are 0 – multiple of 4 -, a 64K cells device if its 16 LSBs are 0 etc.) A Read Command (RD*) which enables the data onto the bus. Normally there is also an Output Enable (OE*) signal. The addressed byte of the memory is output only if CS*=RD*=OE*=0 If the memory is a RAM (read/write memory) another signal is present: write command WR* or WE* which allows to store bus data into the selected memory byte. Obiously this can occur only if CS*=RD*=OE*=0 Needless to say RD* and WR* are mutually exclusive In a system there are normally multiple memory devices in order to implement memory systems bigger that a single device. Multiple devices are therefore needed, each one implementing a portion of the entire memory

14 An example: a 32 Kbytes memory system made with 8K devices
32 Kbytes correspond to a 15 bit address Device selection 32K 8K 14 13 12 Devices internal address Memory device implementing a memory system portion 0000 1FFF 8K 8K 8K CS* = (A14  A13*)* In this case 8K 0K Memory space

15 1MB address space (20 bit address 0-19) - 8 bit parallelism memory 64K bit ROM devices 256K memory bank – Addresses FFFF FFFFF 0000 FFFF 64K 40000 4FFFF 50000 5FFFF 60000 6FFFF 70000 7FFFF B0 B1 B2 B3 512K 7FFFF 40000 256K CS0 = A19* A18 A17* A16* CS1 = A19* A18 A17* A16 CS2 = A19* A18 A17 A16* CS3 = A19* A18 A17 A16 00000 15

16 Memory systems with parallelism > 8 An example: a 16 bit bus
memories internal address Memories physical address = Logic address / 2 i 8 8 Chip pin A0 -> AD1 bus A1 -> AD2 bus ……………………….. h 7 7 Word(4) -> Byteh(2) & Bytel(2) => 2 read Logic Physical (f,e) (f ) (e ) g 6 6 For each bus there must be a ByteEnable* BE0* for bus7-0 e BE1* for bus15-8 f l 5 5 l e l 4 i 4 What about a word at address 7 (not aligned)???? d h 3 g 3 Word(7) -> Byteh(i) & Bytel(h) => 4/3 read Logic Physical (i,h) (i ) (h ) c f 2 e 2 b d 1 c 1 Two memory accesses!!!! a b a The physical memories must be always coupled! For instance 2 x 8K = 16 K ! Logic memory bit 15 8 7 Physical memory High BUS Low BUS 16

17 Memory systems with parallelism > 8 An example: a 16 bit bus
mov al, even_byte_address ; transfer one byte at even address => one bus cycle 8 bit =>BE0* mov al, odd_byte_address ; transfer one byte at odd address => one bus cycle 8 bit => BE1* mov ax, even_word_address ; transfer one word at even address => one bus cycle 16 bit => BE0* and BE!* mov ax, odd_word_address ; transfer one word at odd address => two 8 bit cycles => BE1* and then BE0* 17

18 MEMORIES in a 16 BIT SYSTEM (I.E. 8086)
The routing of byte high external to byte low internal is implemented within the microprocessor chip Physical memories Microprocessor Ri MUX BE1* BE0* Word Odd addresses Even addresses High Byte (odd addr.) Low Byte(even addr.) No transfer A0 of the processor not generated (instead BE0* and BE1*) A1 of the processor connected to chip pin A0 A2 of the processor connected to chip pin A1 etc. etc.

19 EPROM internal addresses
Memory systems with parallelism > 8 A 16 bit bus in a 1MB memory (19 to 0 addresses) Physical memory High BUS Low BUS 64K 7 bit 7 0000h FFFFh EPROM internal addresses 2 x 64K = 128K EPROM1 BE1* EPROM0 BE0* FFFFFh 128K 128K (5H=0101B ; 4H=0100B) 5FFFFh 128K 40000h CSEPROM1= A19*  A18  A17*  BE1 CSEPROM0= A19*  A18  A17*  BE0 In the square the bank selection CS here in positive true form 128K 00000h Logic memory The decoding is performed as if a 8-bit memory were used. Devices (a couple!) (each one half size of the bank) are used and selected by BE0 e BE1

20 (logic even addresses)
Memory systems with parallelism > 8 A 16 bit bus in a 1MB memory (19 to 0 addresses) HIGH BUS (logic odd addresses) Eprom pin Bus Pin EPROM1 BE1* - 64K FFFF FFFE FFFD FFFC 0003 0002 0001 0000 EPROM internal addresses Odd mP addresses LOW BUS (logic even addresses) 0 Eprom Pin 0 Bus Pin 7 EPROM0 BE0* - 64K FFFF FFFE FFFD FFFC 0003 0002 0001 0000 EPROM internal addresses Even mP addresses Logic Memory 5FFFH 5FFFE 5FFFD 5FFFC 5FFFB 40005 40004 40003 40002 40001 40000 128K Logic memory addresses

21 Memory systems with parallelism > 8 A 32 bit bus
Physical Memory Logic Memory i 8 8 h 7 7 Always 4 coupled devices Internal memories physical address is the processor address/4 g 6 6 f 5 5 e 4 4 d 3 c 2 l i 2 b h g f e 1 1 a d c b a bit 31 24 23 16 15 8 7 BUS 3 BE3* BUS 2 BE2* BUS 1 BE1* BUS 0 BE0*

22 N.B. Processor A0 and A1 are not generated
32 BIT bus memories BE3* BE2* BE1* BE0* Word 32 bit Half word low Half word high byte 0-7 byte 15-8 etc. N.B. Processor A0 and A1 are not generated (instead BE0*, BE1*, BE2*, BE3* are generated) Processor A2connected to memories A0 Processor A3connected to memories A1 etc. etc.

23 EPROM internal addresses
32 BIT bus memories (NB the symbol ! before a logic variable is equivalent to asterisk and means negation) Memory bank selection CSEPROM3= !A31  A30  !A29  !A28  !A27  !A26  !A25  !A24  !A23  !A22  !A21  BE3 CSEPROM2= !A31  A30  !A29  !A28  !A27  !A26  !A25  !A24  !A23  !A22  !A21  BE2 CSEPROM1= !A31  A30  !A29  !A28  !A27  !A26  !A25  !A24  !A23  !A22  !A21  BE1 CSEPROM0= !A31  A30  !A29  !A28  !A27  !A26  !A25  !A24  !A23  !A22  !A21  BE0 CS as Positive true form Physical Memory BUS 3 512K 24 31 00000h 7FFFFh EPROM internal addresses EPROM3 BE3* 16 23 EPROM2 BE2* 8 15 EPROM1 BE1* 7 EPROM0 BE0* BUS 2 BUS 1 BUS0 BUS selection Aligned memory FFFFFFFFh 2MB 401FFFFFh 2MB h In the selected bank eleven high address bit are identical 2MB h Logic Memory 4 Memories x 512K= 2MB

24 Generated by the processor
32 BIT bus memories FFFFFFFFh 2MB Physical Memory BUS 3 - D24-31 mP BE3* 512K 7FFFFh Generated by the processor instead of A1 and A0 EPROM3 00000h BUS 2 - D23-16 401FFFFFh 2MB BE2* 512K 7FFFFh h EPROM2 00000h BUS1 - D15-8 BE1* 512K 7FFFFh EPROM1 00000h BUS 0 - D7-0 2MB h BE0* 512K 7FFFFh EPROM0 Logic Memory 00000h Internal addresses

25 Consecutive addresses data are on different devices
32 BIT bus memories Physical Memory (as really implemented) 2MB EPROM3 401FFFFFh 7FFFFh 512K physical addreses of the devices EPROM2 7FFFFh 512K EPROM1 7FFFFh 512K EPROM0 abcdefgh x h 00001h 7FFFFh 512K d 00000h g 00001h c 00000h ------ h e f 00001h h d b 00000h h c h b Consecutive addresses data are on different devices e 00001h h a a 00000h Logic Memory (as seen by the programmer) Byte x at logical address abcdefgh is located at physical address abcdefgh/4 of EPROM i where i is the remainder of the division

26 Exercise A 256K memory RAM (32 bit parallelism) bank starting at address H in a 4GB memory space using the minimum number of devices. What if the parallelism were 64 bit?

27 Exercise A 256K memory RAM (32 bit parallelism) starting at address (aligned) in a 4GB memory space . Address range FFFF. Devices: 8X32 K RAM devices (64K RAM do not exist!!!!) Therefore two banks of 128K : the first implements the range to 8401FFFF and the other the range to 8403FFFF. The 32K memory chips use internally the addresses A14-A0 which are connected to bus addresses BA16-BA2 . Notice that bus address BA17 separates the two banks First bank CSRAM00=(BA31BA30!BA29!BA28!BA27!BA26 .…BA18!BA17!)BE0 CSRAM01=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17!)BE1 CSRAM02=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17!)BE2 CSRAM03=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17!)BE3 Second bank CSRAM10=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17) BE0 CSRAM11=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17) BE1 CSRAM12=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17) BE2 CSRAM13=(BA31BA30!BA29!BA28!BA27!BA26 ….BA18!BA17) BE3 If the parallelism of the memory were 64 bit the 8 CS (CSRAM00..CSRAM07) would NOT be affected by BA17: BE7-BE0 instead would play its role. The 8 devices would implement the entire memory bank and memory chips addresses A14-A0 would be connected to bus addresses BA17-BA3 !! It is the parallelism which changes not the address range!!!


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