1. BTeV Trigger Architecture Vertex 2002, Nov. 4-8 Michael Wang, Fermilab (for the BTeV collaboration)

2. Michael Wang Vertex 2002, BTeV trigger architecture BTeV - a hadron collider B-physics experiment BTeV at C0 CDF D0 p p Tevatron Fermi National Accelerator Laboratory

3. Michael Wang Vertex 2002, BTeV trigger architecture BTeV detector in the C0 collision hall

4. Michael Wang Vertex 2002, BTeV trigger architecture BTeV detector Muon EM Cal Straws & Si Strips SM3 Magnet RICH 30 Station Pixel Detector

5. Michael Wang Vertex 2002, BTeV trigger architecture Pixel detector half-station Multichip module Si pixel detector 50  m 400  m 5 cm 1 cm 6 cm 10 cm HDI flex circuit Wire bonds Sensor module Readout module Bump bonds Si pixel sensors sensor module 5 FPIX ROC’s 128 rows x 22 columns 14,080 pixels (128 rows x 110 cols) 380,160 pixels per half-station total of 23Million pixels in the full pixel detector

6. Michael Wang Vertex 2002, BTeV trigger architecture Simulated B event

7. Michael Wang Vertex 2002, BTeV trigger architecture Simulated B event

8. Michael Wang Vertex 2002, BTeV trigger architecture Primary interaction vertex

9. Michael Wang Vertex 2002, BTeV trigger architecture Primary interaction vertex

10. Michael Wang Vertex 2002, BTeV trigger architecture B decay vertex DsDs K K K  BsBs

11. Michael Wang Vertex 2002, BTeV trigger architecture L1 vertex trigger algorithm 1) Segment finding stage: Use pixel hits from 3 neighboring stations to find the beginning and ending segments of tracks. These segments are referred to as triplets Two stage trigger algorithm: 1.Segment finding 2.Track/vertex finding

12. Michael Wang Vertex 2002, BTeV trigger architecture 1a) Segment finding stage: phase 1 Start with inner triplets close to the interaction region. An inner triplet represents the start of a track. Segment finding: inner tripletes

13. Michael Wang Vertex 2002, BTeV trigger architecture 1b) Segment finding stage: phase 2 Next, find the outer triplets close to the boundaries of the pixel detector volume. An outer triplet represents the end of a track. Segment finding: outer triplets

14. Michael Wang Vertex 2002, BTeV trigger architecture 2a) Track finding phase: Finally, match the inner triplets with the outer triplets to find complete tracks. 2b) Vertex finding phase: Use reconstructed tracks to locate interaction vertices Search for tracks detached from interaction vertices Track/vertex finding

15. Michael Wang Vertex 2002, BTeV trigger architecture Trigger decision Generate Level-1 accept if “detached” tracks in the same arm of the BTeV detector with: (GeV/c) 2 cm Execute Trigger

16. Michael Wang Vertex 2002, BTeV trigger architecture BTeV trigger architecture

17. Michael Wang Vertex 2002, BTeV trigger architecture Pixel data readout Counting RoomCollision Hall Pixel processor Pixel processor Pixel processor FPGA tracker to neighboring FPGA segment tracker to neighboring FPGA segment tracker Pixel stations Optical links Pixel processor time-stamp expansion time ordering clustering algorithm xy table lookup FPIX2 Read-out chip DCB Data combiners Row (7bits)Column (5bits)BCO (8bits)ADC (3bits) sync (1bit) Chip ID (13bits)

18. Michael Wang Vertex 2002, BTeV trigger architecture Level 1 vertex trigger architecture FPGA segment trackers Merge Trigger decision to Global Level 1 Switch: sort by crossing number track/vertex farm (~2500 processors) 30 station pixel detector

19. Michael Wang Vertex 2002, BTeV trigger architecture L1 trigger pre-prototype board 32-bit input 32-bit output FIFO Buffer Manager FPGA CMC connectors

20. Michael Wang Vertex 2002, BTeV trigger architecture L1 pre-prototype with DSP mezzanine cards TI C6711 McBSP GL1/HPI FPGA Hitachi H8S FPGA boot device CF/LCD FPGA ArcNet Hitachi programming Hitachi serial consoles

21. Michael Wang Vertex 2002, BTeV trigger architecture L1 trigger pre-prototype test stand PCI test adapter TI DSP JTAG emulator Xilinx programming cable Hitachi programming ArcNet serial console

22. Michael Wang Vertex 2002, BTeV trigger architecture Level 2/3 trigger R&D Processing nodes from retired Fermilab farm 24-port fanout switch High-density blade server under evaluation

23. Michael Wang Vertex 2002, BTeV trigger architecture End

24. Michael Wang Vertex 2002, BTeV trigger architecture Backup slides

25. Michael Wang Vertex 2002, BTeV trigger architecture L1 vertex trigger efficiencies ProcessEff. (%)Monte Carlo Minimum bias1BTeVGeant B s D + s K - 74BTeVGeant B 0 D* +  - 64BTeVGeant B 0  0  0 56BTeVGeant B 0 J/  s 50BTeVGeant B s J/  *0 68MCFast B - D 0  - 70MCFast B - K s  - 27MCFast B 0 2-body modes 63MCFast (             )