1. Advance Micro Processor
Prepared by: Prof. Ajay Shah
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2. Components of any Computer System
Control – logic that controls fetching/execution of instructions
Memory – area where instructions/data are stored
Input/Output – external interaction with computer
Address bus
C o n t r o l
Memory
Data bus
Input/Output devices
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3. CPU (ALU + Reg + control)
Microprocessors
First microprocessors placed control, registers, arithmetic logic unit in one integrated circuit (one chip).
Data Bus
CPU (ALU + Reg + control)
Address Bus
Memory
I/O
Devices
Control Bus
CPU – Central Processing Unit
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4. Intel x86 Processors
In this chapter will study the Intel x86 general purpose microprocessor family
Instruction set architecture
Assembly language programming
Hardware features of different x86 implementations
Other features of microprocessor systems
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5. The 8086 Microprocessor Family
Characteristics
1)16 bit microprocessor
It means all instructions and registers are operate with 16 bit.
2)16 bit data bus
it can read from or write to memory and I/O ports either 8 or 16 bits at a time
3)20 bit address bus
it can address 220 memory locations
each location is 1 byte (8 bits) wide, thus 16 bit words will require consecutive memory locations
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6. 4) 8086 includes few features, which enhance multiprocessing capability (it can be used with math coprocessors like 8087, I/O processor 8089 etc.
5) Operates on +5v supply and single phase (single line) clock frequency.(Clock is generated by separate peripheral chip 8284).
6) comes with different versions runs at 5 MHz, runs at 8 MHz, runs at 10 MHz
7) It comes in 40-pin configuration with MOS technology having around 20,000 transistors in its circuitry.
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7. Intel x86 Microprocessors
bit Addr. Bus - 1MB of Memory
Addr. Bus - Added Protection Mode
bit regs/busses - Virtual 86 Mode
RISC Core - L1 Cache - FPU
Pentium - Superscalar - Dual Pipeline - Split L1 Cache
Pentium Pro - L2 Cache - Branch Pred. - Speculative Exec.
Pentium MMX - 57 Instructions - Integrated DSP (MMX)
Pentium II MHz Bus - L2 Cache - MMX
Celeron - 66 MHz Bus - True L2 Cache Integration
Pentium III MHz Bus - 70 Internet Streaming SIMD Ext.
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8. 8086 Architecture

9. Processor Architecture Components
Registers : used for storing data values and addresses
Execution units: perform computations (arithmetic, logic) on data
ALU: Arithmetic Logic Unit
Control: logic for fetching, executing instructions
Memory: stores instruction and data
Input/output: external interface with computer system
Instruction Queue: Pipelining

10. EE141
Architecture
The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit (EU).
The BIU fetches instructions, reads and writes data, and computes the 20-bit address.
The EU decodes and executes the instructions using the 16-bit ALU.
Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance.

11. Bus Interface Unit
• The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions:
• Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.
• The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.
This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction.

12. • These prefetching instructions are held in its FIFO queue
• These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. • After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output.

13. The BIU also contains a dedicated adder which is used to generate the 20 bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address.
For example, the physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.
The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write.

14. Generation of 20 bit physical address
The 20-bit Physical address is often represented as,
Segment Base : Offset
OR CS : IP
CS = 3480h IP=1234
CS with Implied Zero
+ IP
3 5 A3 4 H

15. EU Operation An arithmetic operation A logic operation
ALU Data bus
(16 bits) AH AL BH BL CH CL DH DL SP BP SI DI
General purpose
register
ALU
Flag register EU
control
instruction
Depending on the control signal, EU performs one of the following operations:
An arithmetic operation
A logic operation
Storing a data into a register
Moving a data from a register
Changing flag register

16. EXECUTION UNIT
The Execution unit is responsible for decoding and executing all instructions.
The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands.
During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction.
If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle.

17. If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue.
When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions.
Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.

18. Arithmetic Logic Unit (ALU)
n bits A B Y F
Carry
Y= 0 ?
A > B ?
F Y
A + B
A - B
A - 1
A and B
A or B
not A
     
Signal F control which function will be conducted by ALU.
Signal F is generated according to the current instruction.
Basic arithmetic operations: addition, subtraction, 
Basic logic operations: and, or, xor, shifting,

19. Flag register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 - - - - - - - O D I T S Z A P C
Occurrence of Overflow
Carry (Out from digit 7 or digit 15
Even Parity (error detection)
Direction of Change of SI, DI
Auxiliary carry (digit 3 carry into digit 4 generates)
Maskable-Interrupt enable
Trap (halt) Execution
Zero result
Sign (MSB) of result
Flag register contains information reflecting the current status of a microprocessor.
A flag is a flip-flop which indicates some condition produced by executing an instruction, or controls certain operations

20. Status Flags Indicate Current Processor Status
CF Carry Flag Arithmetic Carry/Borrow
OF Overflow Flag Arithmetic Overflow
ZF Zero Flag Zero Result; Equal Compare
SF Sign Flag Negative Result; Non-Equal Compare
PF Parity Flag Even Number of “1” bits
AF Auxiliary Carry Used with BCD Arithmetic
Status and Control Bits Maintained in Flags Register
Generally Set and Tested Individually
9 1-bit flags in 8086; 7 are unused

21. Control Flags Influence the 8086 During Execution Phase
DF Direction Flag Auto-Increment/Decrement
used for “string operations”
IF Interrupt Flag Enables Interrupts
allows “fetch-execute” to be interrupted
TF Trap Flag Allows Single-Step
for debugging; causes interrupt after each operation

22. } } 8086 Register File } AH BH CH DH AL BL CL DL AX BX CX DX CS DS SS7 7
Accumulator AH BH CH DH AL BL CL DL AX BX CX DX
Base
Counter
Data 15
Code Segment CS DS SS ES
Data Segment
Stack Segment
Extra Segment 15 }
Instruction Pointer IP SP BP SI DI }
Stack Pointer
Base Pointer }
Source Index
Destination Index

23. General Purpose Registers AX, BX, CX, DX7 7
Accumulator AX BX CX DX AH BH CH DH AL BL CL DL
Base
Counter
Data
Can Be Used Separately as 1-byte Registers
AX = AH:AL
Temporary Storage to Avoid Memory Access
Faster Execution
Avoids Memory Access
Some Special uses for Certain Instructions

24. AX, BX, CX, DX - Some Specialized Uses7 7
Accumulator AH BH CH DH AL BL CL DL AX BX CX DX
Base
Counter
Data
AX, Accumulator
Main Register for Performing Arithmetic
mul/div must use AH, AL
“accumulator” Means Register with Simple ALU
BX, Base
Point to Translation Table in Memory
Holds Memory Offsets; Function Calls
CX, Counter
Index Counter for Loop Control
DX, Data
After Integer Division Execution - Holds Remainder

25. Data Read/Write process from /To Memory
Word Read
- Each of 1 MB memory address of 8086 represents a byte wide location
- 16 bit words will be stored in two consecutive Memory location
If first byte of the data is stored at an even address , 8086 can read the entire word in one operation.
o For example if the 16 bit data is stored at even address 00520H is 2607
MOV BX, [00520]
8086 reads the first byte and stores the data in BL and reads the 2nd byte and stores the data in BH
BL (00520)
BH (00521)
8086 reads the first byte from location and stores the data in BL and reads the 2nd byte from the location and stores it BH

26. If the first byte of the data is stored at an ODD address, 8086 needs two operation to read the 16 bit data
o For example if the 16 bit data is stored at an odd address 00521H is F520
MOV BX, [00521]
In first operation , 8086 reads the 16 bit data from the location and
stores the data of location in register BL and discards the data of
00520 location
In 2nd operation, 8086 reads the 16 bit data from the location and
stores the data of location in register BH and discards the data of
00523 location
BL (00521)
BH (00522)
For Odd Address
MOV BH, [Addr]
Ex: MOV BH, [ 00521]
8086 reads the first byte from location and ignores it and reads the 2nd byte from the location and stores the data in BH

27. Advantages of memory segmentation
Allow the memory capacity to be 1Mb even though the addresses associated with the individual instructions are only 16 bits wide.
Facilitate the use of separate memory areas for the program, its data, code and the stack.
Easier to manipulate 16 bit numbers than 20 bit numbers…one less byte to deal with.
Permit a program and/or its data to be put into different areas of memory each time the program is executed.

28. Memory
FFFFF
59000
58FFF
Extra
49000
48FFF ES
44000
43FFF
Stack
34000
33FFF SS
30000
2FFFF
Code CS
20000
1FFFF
Data DS
10000
0FFFF
00000

29. Segment Registers
Some of the 220 bytes of addresses are divided in to 4 64KB segments
code segment - CS register stores upper 16 bits of its starting address
where instructions are coming from
stack segment - SS register stores upper 16 bits of its starting address
stores addresses and data while a subprogram is executed
data segment - DS register stores upper 16 bits of its starting address
holds data
extra segment - ES register stores upper 16 bits of its starting address
holds more data
the lower 4 bits are always zero! why?
example: if, the starting address of the code segment is 348A0, then CS contains the value 348AH...this is called the segment base.
the segments can overlap in the case of small program

30. CS, DS, ES, SS - Segment Registers
Contains “Base Value” for Memory Address
Contains “Index Value” for Memory Address
CS, Code Segment
Used to “point” to Instructions
Determines a Memory Address
(along with IP)
Segmented Address written as CS:IP
DS, Data Segment
Used to “point” to Data
Determines Memory Address
(along with other registers)
ES, Extra Segment
allows 2 Data Address Registers
SS, Stack Segment
Used to “point” to Data in Stack Structure (LIFO)
Used with SP or BP
SS:SP or SS:BP are valid Segmented Addresses
IP, Instruction Pointer
Used to “point” to Instructions
Determines a Memory Address (along with CS)
Segmented Address written as CS:IP
SI, Source Index; DI, Destination Index
Used to “point” to Data
Determines Memory Address (along with registers)
DS, ES commonly used
SP, Stack Pointer; BP, Base Pointer
Used to “point” to Data in Stack Structure (LIFO)
Used with SS
SS:SP or SS:BP are valid Segmented Addresses
These can also be used as
General Registers !!!!!!

31. Instruction Pointer Register15
IP Contains Address of NEXT Instruction to be Fetched
Automatically Incremented
Programmer can control with jump and branch

32. Memory Organization

33. Memory Address Calculation
Segment addresses must be stored in segment registers
0000 +
Segment address
Offset
Memory address
Offset is derived from the combination of pointer registers, the Instruction Pointer (IP), and immediate values
Examples 3 4 8 A 2 1 B CS IP +
Instruction address 5 F E SS SP +
Stack address 1 2 3 4 6 DS DI +
Data address

34. Generating Memory Addresses
How can a 16-bit microprocessor generate 20-bit memory addresses?
Left shift 4 bits
FFFFF
16-bit register
0000
Addr1 + 0FFFF
Segment
(64K) +
16-bit register
Offset
Offset
Addr1
20-bit memory address
Segment
address
00000
Intel 80x86 memory address generation
1M memory space

35. Fetching Instructions
Where to fetch the next instruction? CS IP
12352
MOV AL, 0
8086
Memory
Update IP
After an instruction is fetched, Register IP is updated as follows:
IP = IP + Length of the fetched instruction
For Example: the length of MOV AL, 0 is 2 bytes. After fetching this instruction, the IP is updated to 0014

36. Accessing Data Memory Direct addressing: MOV AL, [0300H] 1 2 3 4 6 DS
There is a number of methods to generate the memory address when accessing data memory. These methods are referred to as Addressing Modes
Examples:
Direct addressing: MOV AL, [0300H] 1 2 3 4 6 DS
Memory address
(assume DS=1234H)
Register indirect addressing: MOV AL, [SI] 1 2 3 4 6 5 DS
Memory address
(assume DS=1234H)
(assume SI=0310H)

37. Reserved Memory Locations
Some memory locations are reserved for special purposes Programs should not be loaded in these areas
FFFFF
Locations from FFFF0H to FFFFFH are used for system reset code
Reset
instruction
area
FFFF0
Locations from 00000H to 003FFH are used for the interrupt pointer table
Interrupt
pointer
table
It has 256 table entries
Each table entry is 4 bytes
003FF
256  4 = 1024 = memory addressing space From 00000H to 003FFH
00000

38. Real-Mode memory address space
A 64K segment
Real-Mode memory address space
20 bit physical
address value
1FFFF
The offset or distance of this byte from the segment
register is F000, its address is written as 1000:F000
1F000
Segment value
In, say, CS, DS,
SS, ES etc.
Distance=F000
Segment register
Offset register’s
value, say the one
in IP or SP.
10000
A segment register refers to a fixed memory location,
whose address value= 10h * value of the segment reg.
An offset pointer register (say, IP or SP) is used to hold
the distance or offset value of a byte within the segment;
when the IP or SP is varied, different locations within the
Segment are referred to.
To be replaced by next floid

39. Real mode memory
FFFFF
This location has an effect (distance in bytes) equal to F000 relative to the location pointed by the segment register shown below.
1FFFF
Offset = F000
1F000
64-Kbyte
segment
Segment register
Segment register is usually fixed at a value referring to a fixed location memory while the offset pointer register (e.g. IP, SP, etc.) is varied from time to time according to the program logic.
10000
00000

40. Assembly Language Programming
9/10/2018
PTR and LABEL
Ambiguous size operands
Use PTR to resolve
mov [bx],1
mov word ptr [bx],1
mov [si], 'A'
mov [si],byte ptr 'A'
X label byte
M label word
DW 100
X and M refer to the same address
mov AH,X
mov AH,byte ptr M
mov AX,M
Dr. Tim Margush

41. Assembly Language Programming
9/10/2018
Access to the Stack
mov bp,sp ;BP points to stack top
mov ax,[bp+0] ;top of stack
mov bx,[bp+2] ;next to top of stack
mov [bp+3],ah ;byte at offset 3 in stack
mov [bp-1],ch ;byte above top of stack
... A3 17 FF 20 5F
003A SP
Dr. Tim Margush

42. Assuming that SP=1236, AX=24B6, D1=85C2, and DX=SF93, show the contents of the stack as each of the following instructions is executed:
PUSH AX
PUSH DI
PUSH DX
Solution: 93
SS:1230 5F
SS:1231 C2 C2
SS:1232 85 85
SS:1233 B6 B6 B6
SS:1234 24 24 24
SS:1235
SS:1236
After
PUSH AX
SP=1234
After
PUSH DI
SP=1232
After
PUSH DX
SP=1230
START
SP=1236
Example
Assuming that the stack is as shown below, and SP=18FA, show the contents of the stack and Registers as each of the following instructions is executed:
POP CX
POP DX POP BX
Solution: 23
SS:18FA 14
SS:18FB 6B 6B
SS:18FC 2C 2C
SS:18FD 91 91 91
SS:18FE F6 F6 F6
SS:18FF
SS:1900
After
POP CX
SP=18FC
CX=1423
After
POP DX
SP=18FE
DX2068
After
POP BX
SP=1900
BX=F691
START
SP=18FA

43. Operand Types
Operands are generally considered to be of 3 different types:
immediate
register
memory
An immediate operand is a constant.
A register operand is one of the CPU registers.
A memory operand is a reference to a location in memory.
The 8086 architecture provides 6 possible ways for specifying a memory operand:
direct
direct-offset
register-indirect
indexed
base-indexed
base-indexed with displacement

44. is the offset of a variable.
direct
is the offset of a variable.
count db 20
mov al, count
mov bx, offset count
direct-offset
is the sum of a variable’s offset and a displacement
arrayB db 12, 14, 16, 18
arrayW dw 1000H, 2000H, 3000H
mov al, arrayB + 1
mov ah, arrayB + 2
mov ax, arrayW + 2
mov bx, arrayW + 4
register-indirect
a register that contains the offset of data in memory. Only the SI, DI, BX, and BP registers can be used as indirect operands.
astring db “abcdef”
mov bx, offset astring
add bx, 5
mov dl, [bx]

45. indexed
is the sum of a base or index register and a displacement
mov ax, arrayW[si]
mov ax, arrayW[bx]
base-indexed
is the sum of a base register and an index register
mov ax, [bx+si]
mov ax, [bx][si]
base-indexed with displacement
is the sum of a base register, and index register, and a displacement
mov ax, [bx+si+2]
mov ax, arrayW[bx][si]

46. Assembly Language Programming
8086 Addressing Modes
9/10/2018
There are 24 different addressing modes!
Fortunately, they break down into a smaller number of distinctive categories
Addressing Mode means how the address information in the instruction is used to select a physical address
Increase flexibility of programming language
Common modes specify one or more of Base register, Index register, and Displacement
1.Immediate
4.Indirect
7.Based index
2.Implicit
5.Register
8.Register relative
3.Direct
6.Register Indirect
9.Relative based Indexed
Dr. Tim Margush

47. Addressing modes immediate addressing mode
specify the different ways the processor can access data.
immediate addressing mode
Data accessed quickly from queue. No need of external bus.
Data is a part of instruction.
MOV CX, 437BH
puts the specified value, 437BH directly into CX
register addressing mode
Fastest and compact. No need of external bus.
MOV CX, AX
a register is the source of the operand.
Implicit addressing mode
Data is in a predefined register like in a flag register.
STD , CLC are called zero address instruction.

48. Memory Addressing modes
Memory operands must be transferred from cpu over the bus.
Whenever EU need to read/write operand it must pass an offset value to BIU.
BIU generates 20 bit address.
EU calculates EA by summing displacement, content of base register, and index register.

49. Direct addressing mode
Effective address is taken from displacement field of instruction.
MOV CX, [437AH]
MOV [437AH], CX
Content of CX are copied to memory location whose offset is[437A]

50. Assembly Language Programming
Register Indirect
Assembly Language Programming
9/10/2018
Offset is contained in a register - it is a pointer to a memory location
BP, BX, SI, DI only
The segment register is implied or may be specified.
mov ax,[bp]
mov cl,es:[bx]
mov dl,ds:[si]
mov [di],ax
By default DS is assumed for BX, SI, and DI
SS is assumed for BP
Advantage: one instruction can operate on many different location if value in base/index register is updated.
Dr. Tim Margush

51. 8086 Register Indirect Addressing Modes
Access memory indirectly through a register
For example, mov al, ds:[bx] or mov al, ss:[si]

52. 8086 Based Indexed Addressing Modes
Combinations of register indirect addressing modes and Index addressing mode
Form offset by adding a base register (bx or bp) and an index register (si or di) in form of
mov al, [bx][si]
Let bx contains 1000h and si contains 880h, the above instruction will
load al from location DS:1880h

53. Register relative addressing mode
EA is the sum of 8/16 bit displacement and base/index register.
Mov [BX+1100], AL

54. 8086 Based Indexed Plus Displacement [Relative based inexed]Addressing Mode
If a displacement is specified, the addressing mode is called Base-Index with Displacement
EA is the sum of base register, index register and displacement.
Slight modification of base/indexed addressing modes with addition of an 8 bit or 16 bit constant
Mov CX,[BX+SI+0400]

55. String Addressing mode
Do not use normal memory addressing mode.
SI is assumed to point to first byte and by default segment is DS.
DI is assumed to point to first byte of destination string and by default segment is ES.
In repeated string operation automatic adjustment is done with the help of Direction Flag.

60. Interrupts 2 Types of Interrupts:
An interrupt is an event that occurs while the processor is executing a program
The interrupt temporarily suspends execution of the program and switch the processor to executing a special routine (interrupt service routine)
When the execution of interrupt service routine is complete, the processor
resumes the execution of the original program
2 Types of Interrupts:
External - generated outside CPU by other hardware
Internal - generated within CPU as a result of an instruction or operation
Flag bits IF (interrupt flag) and TF (trap flag), are also used with the interrupt structure and special return instruction IRET
An interrupt service procedure/routine (ISP or ISR) is the subroutine called for execution by the hardware interrupt.

61. Interrupt Processing IRET At the end of every normal instruction,
mP checks for
interrupts- in this order:
1. Internal Interrupts from
results of execution,
e.g. overflow, divide by 0
2. Single step
3. NMI
4. INTR
5. INT n instructions
Restores original
Interrupt status
IRET
Higher
Priority

62. When an Interrupt Occurs (Assume Real Mode)
1. The Flags register is pushed onto the stack
2. Both the interrupt (IF) and trap (TF) flags are cleared. This disables the INTR input and the trap from interrupting the interrupt being handled
3. The code segment register (CS) is pushed onto the stack.
4. The instruction pointer (IP) is pushed onto the stack.
5. The interrupt vector contents are fetched from the interrupt vector table and then placed into the IP and CS so that the next instruction executes at the interrupt service procedure addressed by the vector.

63. Interrupt Service Routine
TEMP
push
Flags 1
Complete
Current
Instruction
Internal
Interrupt
Set
TEMP=TF
Execute
ISR
YES NO
IF=0
TF=0
pop
IP and CS
NMI
YES NO
INTR IF
YES 1
push
CS and IP
popf NO TF 1
acknowledge
interrupt
call
ISR
Resume
Interrupted
Procedure
Read Type
Code #
Fetch
Next
Instruction
NMI
YES NO

64. Interrupt Vectors
The location of each ISR program (Interrupt Service Routine) in memory is stored in an interrupt vector/descriptor table:
- In the real mode:
As a 4-byte far address (to specify a segment and an offset)
- In the protected mode:
As an 8-byte interrupt descriptor
A total of 256 different interrupt type numbers for software and hardware interrupts
ISRs are identified by the interrupt type numbers (0-255d)
Stored in: (use interrupt number as a pointer to determine interrupt vector/descriptor)
 Real Mode: The first 1024 B of RAM (256 x 4 B) at the bottom of the memory map
(for the 8086: FF)
 Protected Mode: In the interrupt descriptor table (IDT) (2 KB = 256 x 8B)
How does the processor know the interrupt number?:
- Software interrupts: Using the xx in the INT xx instruction
- INTR Hardware interrupts: Interrupting device places the vector number (xx) on the data bus in response to the interrupt acknowledge (#INTA)
- NMI is treated as a software interrupt (its xx = 2 is fixed & known to the processor)

65. Interrupt Vector Table in the Real Mode
Top 224 Interrupt Vectors:
For user, Hardware and Software
First 32 Interrupt Vectors:
Reserved for system use
256 Interrupt Vectors
Page Fault
(Page required is not in
Physical memory)
Interrupt type number 00H-FFH
NMI is internally decoded as
Type 2 interrupt. Does not need to provide
an external vector like other hardware
interrupts
Starting address
of interrupt vector = 4 n
Where n is the vector type
4 bytes Far address for each vector
For debugging
If Trap flag (TF) F is set
16-bit Segment
address
16-bit Offset
address

66. Example An easy way to multiply by 4 Segment Interrupt Vector
1000
E309
An easy way to
multiply by 4
Segment
Interrupt Vector
for type 41H interrupt
Offset

67. Hardware Interrupts Software Interrupts Conditional
INTR & NMI Hardware inputs
#INTA Hardware ACK for INTR interrupts only
IF (Interrupt Flag) enables/disables INTR interrupts
For INTR, interrupt number n supplied to the processor by the interrupting hardware in an INTA read cycle
For NMI: n = fixed at 2
Software Interrupts
INT n Instruction, n = interrupt number:
Special cases:
 n = 1: Single step (trap)
Enabled if TF (Trap flag) bit in Flags is set
 n = 3: INT 3 (Breakpoint)
 n = 4: INTO (Overflow)
 n = 5: BOUND (Check limits)
For both:
ISR ends with the IRET Instruction to return from interrupt
Conditional

68. Software Interrupts Conditional:
- INTO (interrupt type 4): on Overflow (the OF flag bit)
- BOUND (type 5): on the result of comparing the contents of a register with the contents of two successive words in memory, e.g.
BOUND AX, DATA
causes interrupt type 5 if AX contents are outside the range specified by the 4 bytes
i.e., [AX] < {[DATA], [DATA+1]} or [AX] > {[DATA+2], [DATA+3]}
Unconditional:
 INT n: Executes the interrupt with the vector type n
- Instruction takes 2 bytes: a byte for the opcode and a byte for n
e.g. INT 80H  Start of the 4-byte vector address = 4 x 80H = 200H (200H – 203H)
 INT 3: is a special case of INT n which fits into one byte only. Useful in inserting a break point in the software for debugging purposes

69. Software/Hardware Interrupts
Return from Interrupt (last instruction in the ISR)
IRET (instead of RET for returning from subroutine)
Retrieves from the stack:
- Return address (CS & IP)
- The Flags register

70. Software Interrupts
The INT instruction can be used to do one of the 256 interrupts[Type 0-255]
Example: INT0 – Divide by zero
Using this we can call routines from different programs in system.

71. Dedicated Interrupts Type1 – single step interrupt
In this it will execute one instruction and stop.
And wait for further direction from user.
One can examine the content of memory/register.
No direct instruction to set/reset trap flag.
Copy flags onto stack, set TF bit on stack, pop the flag.

72. Type2 - NMI Non maskable with highest priority hardware interrupt.
Edge triggered input is synchronized with CPU clock and must be active for two clock cycle.
Low to High transition.
Location in Interrupt vector table:
Type no * 4 = location -> 00008h
00008h/09h = get new IP
0000Ah/Bh = get new CS
Typical applications: Important system faults, e.g.
 Power failure, so that processor can save registers, e.g. into a flash memory

73. Type3 – Breakpoint interrupt
Location in Interrupt vector table:
Type no * 4 = location -> 0000Ch
0000Ch/0Dh = get new IP
0000Eh/0Fh = get new CS

74. Priority of 8086 Interrupts
NMI
Divide error, INT n, INTO
INTR
Single Step

75. 8086 External Interrupt Connections
NMI - Non-Maskable Interrupt INTR - Interrupt Request
Programmable Interrupt Controller (part of chipset)
NMI Requesting Device
NMI
8086 CPU
Intel
8259A
PIC
INTR
Interrupt Logic
int
into
Divide
Error
Single
Step
Software
Traps

76. .model small
.data
array db 2h,6h,5h,12h
.code
start: mov
mov ds,ax
lea BX,array
BACK:
mov dl,[BX+DI]
mov al,dl
INC DI
JNZ BACK
end start

77. Minimum and Maximum Operation modes
Intel 8088 (8086) has two operation modes:
Minimum and Maximum Modes:
• The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single microprocessor configuration.
• The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi micro processors configuration.
Minimum Mode Maximum Mode
8086 generates control signals for memory and I/O operations
It needs 8288 bus controller to generate control signals for memory and I/O operations
Some functions are not available in minimum mode
It allows the use of 8087 coprocessor; it also provides other functions
Compatible with 8085-based systems

78. EE141
Pinout Diagram

82. RD’ TEST’ When asserted it indicates a read operation is happening.
It is an active low output signal.
MN/MX’
If HIGH, single processor system.
If LOW, multiprocessor system.
TEST’
It is an active low input line dedicated for 8087 coprocessor.
In min. mode it is connected to GND.
In max. mode when coprocessor is busy it makes this pin high.
This pin is tested by the WAIT instruction,
- If TEST is a logic 0, the WAIT instruction functions as an NOP.
- If TEST is a logic 1, the WAIT instruction waits for TEST to become a logic 0.

83. Minimum mode operation
EE141
Minimum mode operation
Ground
Power Supply
5V  10%
Clock
Duty cycle: 33%
Reset
Registers, seg regs, flags
CS: FFFFH, IP: 0000H
If high for minimum 4 clks

84. CLK
Clock input to the processor from external clock generator due to unavailability of on chip clock.
33% duty cycle.
RESET:
It causes the processor to immediately terminate its present activity. The signal must be active HIGH for at least four clock cycles. It restarts execution MN/MX.
It clears all flags, Instruction queue, DS,ES,SS and sets CS.
READY
READY is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer.
When READY is logic 0 the microprocessor inserts wait states into the timing of the processor.

85. Minimum mode operation ( Conti..)
EE141
Minimum mode operation ( Conti..)
Address/Data Bus:
Contains address bits A15-A0 when ALE is 1 & data bits D15 – D0 when ALE is 0.
Address Latch Enable:
When high, multiplexed address/data bus contains address information.

86. ALE
Address Latch Enable. A HIGH on this line causes the lower order
16bit address bus to be latched that stores the addresses and then, the lower order 16bit of the address bus can be used as data bus.
Demultiplex the address data line by latching address.
AD15±AD0
ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address and data bus.
And contain the rightmost 8 bits of the memory address or I/O port number whenever ALE is active (logic 1)
or data whenever ALE is inactive (logic 0)
It gives the address A16-A0 during T1 of every machine cycle.
It gives data D15-D0 after T1 of machine cycle.

87. Minimum mode operation ( Conti..)
EE141
Minimum mode operation ( Conti..)
INTERRUPT
Non-maskable interrupt
Interrupt acknowledge
Interrupt request

88. INTR INTERRUPT REQUEST:
It is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.
INTA
On receiving an interrupt on INTR line processor execute 2 INTA pulses.
1st: Interrupt is accepted. Interrupt Acknowledge from the MP
2nd: Sends vector no. to processor on data bus
NMI NON-MASKABLE INTERRUPT:
It is an edge triggered input which causes an interrupt request to the MP. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software.
Transition from low to high on this pin causes interrupt at the end of current instruction.

89. Minimum mode operation ( Conti..)
EE141
Minimum mode operation ( Conti..)
Direct Memory Access
Hold acknowledge
Hold

90. Hold input requests a direct memory access (DMA).
HOLD : The 8086 has a pin called HOLD. This pin is used by external devices to gain control of the busses.
In response 8086 completes current bus cycle and release system bus.
Hold input requests a direct memory access (DMA).
if HOLD signal is a logic 1, the microprocessor stops executing software and places address, data, and control bus at high-impedance
if a logic 0, software executes normally
HLDA :
When the HOLD signal is activated by an external device, the 8086 stops executing instructions and stops using the busses. This would allow external devices to control the information on the.

91. Minimum mode operation ( Conti..)
EE141
Minimum mode operation ( Conti..)
S6: Logic 0.
S5: Indicates condition of IF flag bits.
S4-S3: Indicate which segment is accessed during current bus cycle:
Address/Status Bus
Address bits A19 – A16 & Status bits S6 – S3

92. Minimum mode operation ( Conti..)
EE141
Minimum mode operation ( Conti..)
BHE#, A0:
0, 0: Whole word (16-bits)
0,1: High byte to/from odd address
1,0: Low byte to/from even address
1,1: No selection
Bus High Enable/S7
Enables most significant data bits D15 – D8 during read or write operation.
S7: Always 1.

93. A16/S3…A19/S6
It gives the address during T1 of every machine cycle.
T2 onwards this lines works as status signals.
S5 gives status of Interrupt enable Flag.
S6 goes low when 8086 controls the shared system bus.
S3 S Segment accessed
Extra Seg.
Stack Seg.
0 Code Seg.
Data Seg.
BHE’/S7
BHE’ and A0 used together to access a word/byte from memory.
S7 reserved for future development.

94. Minimum mode operation ( Conti..)
EE141
Minimum mode operation ( Conti..)
Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
Min mode pins

95. Other minimum mode pins
M/IO’ : Differentiate between the Memory and I/O operation.
A LOW on this pin indicated I/O operation and a HIGH indicated a Memory Operation.
WR’: Indicate s write operation when pin is low.
Used with M/IO’ to write memory.
DEN’: Enable data transceiver.
INTA’: It is issued in response to an interrupt on INTR line.
DT/R’:
Data transmit/receive indicates that the data bus is transmitting or receiving information.

96. Minimum mode operation ( Conti..)
EE141
Minimum mode operation ( Conti..)
Read Signal
Write Signal
Memory or I/0
Data Bus Enable
Used by external data bus buffers

97. EE141
Maximum mode

98. Maximum mode operation ( Conti..)
EE141
Maximum mode operation ( Conti..)
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access
101: read memory
110: write memory
111: none -passive
Status Signal
Inputs to 8288 to generate eliminated signals due to max mode.

99. Maximum mode operation ( Conti..)
EE141
Maximum mode operation ( Conti..)
DMA Request/Grant

100. Maximum mode operation ( Conti..)
EE141
Maximum mode operation ( Conti..)
Lock Output
Used to lock peripherals off the system
Activated by using the LOCK: prefix on any instruction
Lock Output

101. Maximum mode operation ( Conti..)
EE141
Maximum mode operation ( Conti..)
QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of opcode
Queue Status
Used by numeric coprocessor (8087)

102. Maximum Mode S2’,S1’ and S0’ RO’/GT1’ and RO’/GT0’ LOCK’ QS1’ and QS0
These status bits indicate the function of the current bus cycle.
It is given to 8288.
RO’/GT1’ and RO’/GT0’
Request/grant pins used for DMA during maximum mode operation.
External master sends active low pulse to request for control over system bus.
LOCK’
Used to lock peripheral off the system.
QS1’ and QS0
Queue status bits.

103. The combination of some of the pins of the microprocessor indicates several different functions:
Bus cycle status;
Bus control functions;
Queue status.

104. The Clock
The clock signal is very important to the operation of a microprocessor circuit.
It synchronizes the sequential activities of the CPU and the system
Not all devices use a clock signal (eg. PPI)

105.   CLOCK GENERATOR (8284A)
This section describes the 8284A clock generator and the RESET signal.
also introduces the READY signal for 8086/8088
With no clock generator, many circuits would be required to generate the clock (CLK).
Min. clock freq of 2 MHz has been decided by keeping the refreshing cycle of dynamic RAM cells.
8284A provides the following basic functions:
clock generation; RESET & READY synch;
TTL-level peripheral clock signal
Fast rise and fall times ( <10ns )
Logic 0: -0.5 to 0.6 V
Logic 1: 3.9 to 5.0 V
Duty cycle of 33%

106. 8284 Clock Generator

107. GND VCC X1 and X2 The ground pin connects to ground.
The crystal oscillator pins connect to an external crystal used as the timing source for the clock generator and all its functions.
Crystal freq should be equal to 3 times required clock freq.
Fclk = 5MHz then Crystal freq= 15MHz
GND
The ground pin connects to ground.
VCC
This power supply pin connects to +5.0 V with a tolerance of ±10%.

108. F/C
The frequency/crystal select input chooses the clocking source for the 8284A.
if held high, an external clock is provided to the EFI input pin
if held low, the internal crystal oscillator provides the timing signal
The external frequency input is used when the F/C pin is pulled high.
EFI supplies timing when the F/C pin is high.
EFI:
External frequency input. Signal can be used as the clocking source to the 8284A instead of the crystal oscillator.

109. CLK
The clock output pin provides the CLK input signal to 8086/8088 and other components.
output signal is one third of the crystal or EFI input frequency
33% duty cycle required by the 8086/8088
fclock = fxtal/3 = fEFI/3
OSC:
EFI To other mPs 3 2
PCLK
to Per
XTAL
or EFI
PCLK
CLK
to mP
The peripheral clock signal is one sixth the crystal or EFI input frequency.
PCLK output provides a clock signal to the peripheral equipment in the system .
(1/2 clock freq) with 1:2 duty cycle
fpclk = fxtal/6 = fEFI/6
OSC: Oscillator output.
Same frequency as crystal or EFI. Connect to EFIs on other 8284As in multiprocessor systems (synchronized clocks)
fosc = fxtal= fEFI

110. AEN1 and AEN2
The address enable pins are provided to qualify bus ready signals, RDY1 and RDY2.
used to cause wait states
Wait states are generated by the READY pin of 8086/8088 controlled by these two inputs.
Ready:
It is an output pin that connects to the 8086/8088 READY input. synchronized with the RDY1 and RDY2 inputs
RDY1 and RDY2
The bus ready inputs are provided, in conjunction with the AEN1 & AEN2 pins, to cause wait states in 8086/8088.

111. CSYNC
The clock synchronization pin is used when the EFI input provides synchronization in systems with multiple processors.
if internal crystal oscillator is used, this pin must be grounded
ASYNC
The ready synchronization selection input selects either one or two stages of synchronization for the RDY1 and RDY2 inputs.

112. RES Reset input is an active-low input to 8284A. Reset :
often connected to an RC network that provides power-on resetting .
Reset :
It is an active OUTPUT high pin which is used to reset 8086 family processors.
Output is connected to the 8086/8088 RESET input pin.

113. Power on RESET circuit
When power is switch on there are some spikes in its output for sometime. It can cause to change default value of registers.

114. Operation of the Power on Reset Circuit
Initially the capacitor is uncharged. When power is switched on, the Reset signal is at logic 1. The capacitor starts charging with time constant (10K*10uF). When the voltage across the capacitor becomes equal to the minimum High voltage of the 8284 (2V), the Reset signal goes to logic 0.
If the Reset button is pressed, the capacitor is discharged through the switch. When the Button is released, the capacitor starts charging as before.
Resistor R1 is used to reduce the current through C1 when the Reset button is pressed, thus avoid damaging C1. The diode is used to short circuit R1 during switch off, thus discharge C1 fast.

115. Typical Application of the 8284A for clock and Reset signal generation
frequency, f
f/3
2.5 MHz
PCLK
Grounded when
Xtal Osc is used
f/6
OSC
15 MHz f R
RESET
Synced
To CLK C
RC circuit for
automatic Reset on power up
Manual
Reset
push button
Switch
50 ms
Minimum
Effective
Digital
#RES Input
RC time constant large enough
for 50 ms min Reset pulse
at worst trigger conditions (1.05 V Threshold)

116. Clock/Reset/Ready Circuit
The 8284 chips serves three purposes:
Generates the main clock (CLK) for the processor (fc/3 with 33% duty cycle) and the clock for the peripheral devices (fc/5).
Provides the Reset pulse according to the state of the RC circuit connected at the RES input.
Provides the Ready signal to insert wait states whenever the processor is accessing slow memory or peripheral I/O ports.

117. T States Why are there T states?
In the 8086/8088, the address and data lines are multiplexed.
The microprocessor needs time to change the signals during each bus cycle.
Memory devices need time to decipher the address value and then read/write the data (access time)

118. Operation of the Clock Section
Crystal oscillator has two inputs: X1 and X2.
if a crystal is attached to X1 and X2, the oscillator generates a square-wave signal at the same frequency as the crystal
The square-wave is fed to an AND gate & an inverting buffer to provide an OSC output.
The OSC signal is sometimes used as an EFI input to other 8284A circuits in a system.
Figure shows how an 8284A is connected to the 8086/8088.

119. Clock Generator (8284A): Block Diagram
Starts 4 clock pulses max after power up
Must be kept High for at least 50 ms
Hysteresis to avoid
jitter due to slowly
varying inputs
Schmitt trigger
RESET
Switch/RC circuit
Active High,
to mP
Synchronize
with – ive clock edge
Crystal
Inverting buffer
Select clocking source
Use as EFI in
Multiprocessor
systems
CLOCK & Sync
Select Crystal Osc
or EFI
 3
 2
Peripheral
Clock. f = 1/6th
of crystal or EFI
Frequency,
1:2 duty cycle
External Frequency I/P
Synchronize clock if EFI is used with multiprocessor systems
To processor
CLK input.
f = 1/3rd of
crystal or EFI
Frequency,
1:3 duty cycle
READY
0 = 2 stages, 1 = 1 stage of synchronization

120. Operation of the Reset Section
The reset section of 8284A consists of a Schmitt trigger buffer and a D-type flip-flop.
the D-type flip-flop ensures timing requirements of 8086/8088 RESET input are met
This circuit applies the RESET signal on the negative edge (1-to-0 transition) of each clock.
8086/8088 microprocessors sample RESET at the positive edge (0-to-1 transition) clocks.
thus, this circuit meets 8086/8088 timing requirements

121. 8282/8283 Octal Latch
It is a register with specific purpose. This group of D flip flops is used to hold the values to be output to other devices.
Multiplexed bus:
Presence of address on bus indicated by ALE.
ALE as strobe is used to enable the external latch to store address.
ALE goes low before address disappears from bus.
Now processor will output data on bus.
8 bit bipolar latch so 3
Latches for 20 bit add.

124. 8282 non inverting latch
8283 inverting latch
STB is an active high input which latches the input appearing
on 8 input lines DI0 to DI7 into latch.
OE is an active low signal which enables output buffers.
If OE=1 latch outputs are in tri state.

126. 8286 Octal Bus Transceiver
Used to obtained 16 bit data from multiplexed bus.

127. A0-A7: local bus data lines. Act as input or output lines
A0-A7: local bus data lines. Act as input or output lines depends on T pin.
If T=1 then act as input lines.
B0-B7: system bus data lines. Act as input or output lines depends on T pin.
If T=1 then act as output lines.
T[Transmit]: Input pin of It controls direction of
transceiver.
OE[output enable]: Active low input. It is used for enabling appropriate driver to put his data on respective bus.
If OE=1 then outputs in tri state.

128. Multiplexed bus: 8 bit transceiver. so, 2 8286 ICs are required.
B output act as de multiplexed data bus.
It allows bidirectional data transfer.
T pin is connected to DT/R output of 8086.
DT/R =0 , T=0, B lines act as input lines & A lines act as output lines. Data will flow from memory/ports to Read operation.
OE lines connected to DEN line to enable/disable transceiver.

129. De multiplexing Address and Data Bus

130. IC 74138 decoder for Control Bus
IC used to convert these RD, WR, M/IO lines into following four signals.
MEMR memory read
MEMW memory write
IOR I/O read
IOW I/O write

131. 8288 Bus controller Used in maximum mode configuration.
Accepts CLK signal along with s0, s1, s2 outputs of 8086 and generates command, control and timing signals at its output.
Provides bipolar bus drive capability and optimizes system performance.

132. 8086 Timing diagrams
All operations are carried out in synchronized manner.
Timing diag. is required to understand every operation.
T state: One complete cycle of clock is called T state.
measured from falling edge to falling edge.
Machine Cycle: Basic operation such as reading a byte from I/O port or writing a byte to memory is called a machine cycle.
It is a made up of many T states.
Instruction Cycle: The time a microprocessor needs to fetch and execute one entire instruction is known as an Instruction cycle.

133. WAIT states
Slow peripheral devices will get some time to put their valid data on data bus.
8086 will be slow down to work successfully with slow peripherals.
READY input is passed to 8086 through 8284 to synchronize the ready signal.
8086 will continue to insert wait states as long as READY is low.
All buses will freeze during wait states means signals remains same.

134. Minimum System block diagram

135. Minimum mode operation ( Conti..)
EE141
Minimum mode operation ( Conti..)

136. READ cycle

137. Minimum mode operation ( Conti..)
EE141
Minimum mode operation ( Conti..)

138. WRITE cycle

139. Maximum System block diagram

142. 8088 microprocessor 6 bit data bus 20 address lines
Capable of operating in single processor and multiprocessor.
Multiplexed address/data bus.
Architecture of 8088 is similar to 8086 except queue.
External data bus is 8 bit[D0-D7]. So no even odd memory
banks.
Queue is of 4 byte length instead of 6 byte. bcoz 8088 can
only fetch one byte at a time.