1. In The Name of God
Design of A Sample And Hold Circuit Based on The Switched Op-Amp Techniques
M.Rashtian: Faculty of Civil Aviation Technology College
O.Hashemipour: Faculty of shahid baheshti university
K.Navi: Faculty of shahid baheshti university

2. Charge Injection & Clock Feedthrough
Main Idea
Charge Injection and Clock Feedthrough Cancellation
Dependence of Device Mismatches
Loading effect of indirect switches
Results
Main Source of Error

3. Charge Injection & Clock Feedthrough

4. Main Idea

5. QM2=-W2L2Cox(Vgs2-Vtn)=-W2L2CoxVeff2
(1)
QM3=W3L3Cox|(Vgs3-Vtn)|=W3L3CoxVeff3
(2)
IDM3=IDM2+ICh=IDM2+ChωVIMCos(ωt)
(3)
Canceling the charges (QM2+QM3=0) results in:
Veff2 and Veff3 are designed the same. (W3L3=W2L2)

6. Dependence of Device Mismatches
The circuit dependence on device mismatches is not critical since the total injected charge into the hold capacitor (Qtotal) is given by equation (5):
Qtotal = (W3L3-W2L2) Cox (Veff3-Veff2)
(5)
(6)

7. Loading effect of indirect switches
It is crucially important that both output transistors turn off simultaneously. Effective Capacitor of M5,6 ⍺ W5,6 so W5 must be equal to W6 . For having equal drain current below equation have to satisfied:
(7)

8. Complete designed circuit
Special property:
Low impedance in every node except in the holding node.

9. High Linear Output Stage
0.5β13 (Vgs13-Vtp)2 = 0.5β14 (Vgs14-Vtp)2
M13 and M14 are the same. So:
Vsg13 = Vsg14 =Vdd - Vin = Vout
AV = -1

10. Results (1) Comparison of input and output
Input voltage at 50KHz and 1v(p-p)
_______ Output sampled signal

11. FFT of output at input amplitude of 1 volt (p-p) at frequencies of
Results (2)
FFT of output at input amplitude of 1 volt (p-p) at frequencies of
a) KHz
b) KHz

12. Table 1: Overal specification of proposed sample and hold
Results (3)
Table 1: Overal specification of proposed sample and hold
1000mv (p-p)
Input Maximum Amplitude
2.6v
Power Supply
1.3v
Vref
1.35mw
Power Dissipation
74db
Dynamic Range
104 ns
Acquisition Time at 1v Step and 0.2mv error
1MHz
Sampling Frequency
79db
Opamp dc Gain
53o
Opamp Phase margin
34.5v/µs
Opamp SR

13. The Main Source of Error
Input-Output Phase Delay (φ)
Delay Error =Vo-Vi = Cos(ωt) Sin(φ/2)
If Vi=0.5 Cos(2π105 t)→φ=-0.16&
Max Delay Error=0.5sin(0.84)
=0.68mv
This error is approximately same to simulation result.
Frequency response of closed loop op-amp

14. Thanks
for your attention
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