1. Jimin Kim Thinh Nguyen Sen Mao
UW VME GROUP
Jimin Kim Thinh Nguyen Sen Mao

2. Outline Initial plan at the beginning of quarter
Outline of the readout chain
Current progress
Issues
Proposed plan

3. Initial Plan
Study the ePP0, pp0_testboard and their functionalities, connections.
Have a complete read-out chain by the end of quarter.

4. Test System Readout Chain

5. ePP0 card
Upper half of the ePP0 is used to route clock and command signals to modules.
The other half transfer module data back to eBOC
Consists of LVDS drivers and receivers
Uses Altera Flex6000 FPGA (same on eBOC)
Connect to eBOC via sub-D connectors

7. On-board PROM On-board programmable Read only Memory
PROM file programmed on a PROM chip (EPC1PC8) using a PROM device programmer with Quartus II software

9. Epp0_Testboard
Replaces a real PP0
VDDA = 1.6V
VDD = 2V

11. Injection circuit
4000 e- permits efficient tracking for m.i.p of 19,300 e- at beginning to 10,000 e- at the end

12. Injection charge test

13. Digital Scan

14. Digital Scan

15. Testing tools
Use STcontrol or similar software to send trigger signals to the FPGA.
Use oscilloscope to monitor the output signals from the ROD
Digital test to check for error rate (Single Event Generator)

16. Plan
Have a complete read-out chain for further testing
Test at 40Mb/s