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CS 152 Computer Architecture and Engineering Lecture 3 - From CISC to RISC
Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley CS252 S05
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Instruction Set Architecture (ISA) versus Implementation
ISA is the hardware/software interface Defines set of programmer visible state Defines instruction format (bit encoding) and instruction semantics Examples: MIPS, x86, IBM 360, JVM Many possible implementations of one ISA 360 implementations: model 30 (c. 1964), z990 (c. 2004) x86 implementations: 8086 (c. 1978), 80186, 286, 386, 486, Pentium, Pentium Pro, Pentium-4 (c. 2000), AMD Athlon, Transmeta Crusoe, SoftPC MIPS implementations: R2000, R4000, R10000, ... JVM: HotSpot, PicoJava, ARM Jazelle, ... 1/29/2009 CS152-Spring’09 CS252 S05
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Styles of ISA Accumulator Stack GPR CISC RISC VLIW Vector
Boundaries are fuzzy, and hybrids are common E.g., 8086/87 is hybrid accumulator-GPR-stack ISA Many ISAs have added vector extensions 1/29/2009 CS152-Spring’09
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Styles of Implementation
Microcoded Unpipelined single cycle Hardwired in-order pipeline Out-of-order pipeline with speculative execution and register renaming Software interpreter Binary translator Just-in-Time compiler 1/29/2009 CS152-Spring’09
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Last Time in Lecture 2 Stack machines popular to simplify High-Level Language (HLL) implementation Algol-68 & Burroughs B5000, Forth machines, Occam & Transputers, Java VMs & Java Interpreters General-purpose register machines provide greater efficiency with better compiler technology (or assembly coding) Compilers can explicitly manage fastest level of memory hierarchy (registers) Microcoding was a straightforward methodical way to implement machines with low gate count 1/29/2009 CS152-Spring’09 CS252 S05
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A Bus-based Datapath for MIPS
rs rt rd ExtSel IR Opcode ldIR Imm Ext enImm 2 zero? A B OpSel ldA ldB ALU enALU control 2 enMem MA addr data ldMA Memory busy MemWrt RegWrt enReg addr data rs rt rd 32(PC) 31(Link) RegSel 32 GPRs + PC ... 32-bit Reg 3 Bus 32 Microinstruction: register to register transfer (17 control signals) MA PC means RegSel = PC; enReg=yes; ldMA= yes B Reg[rt] means RegSel = rt; enReg=yes; ldB = yes 1/29/2009 CS152-Spring’09 CS252 S05
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MIPS Microcontroller: first attempt
PC (state) Opcode zero? Busy (memory) Control Signals (17) s 6 Program ROM addr data latching the inputs may cause a one-cycle delay How big is “s”? ROM size ? Word size ? = 2(opcode+status+s) words next state = control+s bits 1/29/2009 CS152-Spring’09 CS252 S05
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Reducing Control Store Size
Control store has to be fast expensive Reduce the ROM height (= address bits) reduce inputs by extra external logic each input bit doubles the size of the control store reduce states by grouping opcodes find common sequences of actions condense input status bits combine all exceptions into one, i.e., exception/no-exception Reduce the ROM width restrict the next-state encoding Next, Dispatch on opcode, Wait for memory, ... encode control signals (vertical microcode) 1/29/2009 CS152-Spring’09 CS252 S05
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MIPS Controller V2 ext Control ROM +1 PC (state) jump logic zero PC
Control Signals (17) Control ROM address data +1 Opcode ext PC (state) jump logic zero PC PC+1 absolute op-group busy PCSrc input encoding reduces ROM height JumpType = next | spin | fetch | dispatch | feqz | fnez next-state encoding reduces ROM width 1/29/2009 CS152-Spring’09 CS252 S05
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Jump Logic PCSrc = Case JumpTypes next PC+1
spin if (busy) then PC else PC+1 fetch absolute dispatch op-group feqz if (zero) then absolute else PC+1 fnez if (zero) then PC+1 else absolute 1/29/2009 CS152-Spring’09 CS252 S05
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Instruction Fetch & ALU:MIPS-Controller-2
State Control points next-state fetch0 MA PC fetch1 IR Memory fetch2 A PC fetch3 PC A + 4 ... ALU0 A Reg[rs] ALU1 B Reg[rt] ALU2 Reg[rd]func(A,B) ALUi0 A Reg[rs] ALUi1 B sExt16(Imm) ALUi2 Reg[rd] Op(A,B) next spin dispatch next fetch next fetch 1/29/2009 CS152-Spring’09 CS252 S05
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Load & Store: MIPS-Controller-2
State Control points next-state LW0 A Reg[rs] next LW1 B sExt16(Imm) next LW2 MA A+B next LW3 Reg[rt] Memory spin LW4 fetch SW0 A Reg[rs] next SW1 B sExt16(Imm) next SW2 MA A+B next SW3 Memory Reg[rt] spin SW4 fetch 1/29/2009 CS152-Spring’09 CS252 S05
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Branches: MIPS-Controller-2
State Control points next-state BEQZ0 A Reg[rs] next BEQZ fnez BEQZ2 A PC next BEQZ3 B sExt16(Imm<<2) next BEQZ4 PC A+B fetch BNEZ0 A Reg[rs] next BNEZ feqz BNEZ2 A PC next BNEZ3 B sExt16(Imm<<2) next BNEZ4 PC A+B fetch 1/29/2009 CS152-Spring’09 CS252 S05
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Jumps: MIPS-Controller-2
State Control points next-state J0 A PC next J1 B IR next J2 PC JumpTarg(A,B) fetch JR0 A Reg[rs] next JR1 PC A fetch JAL0 A PC next JAL1 Reg[31] A next JAL2 B IR next JAL3 PC JumpTarg(A,B) fetch JALR0 A PC next JALR1 B Reg[rs] next JALR2 Reg[31] A next JALR3 PC B fetch 1/29/2009 CS152-Spring’09 CS252 S05
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Implementing Complex Instructions
busy zero? Opcode ldIR OpSel ldA ldB 32(PC) ldMA 31(Link) rd rt 2 rs RegSel MA 3 rd rt IR addr addr A B rs 32 GPRs + PC ... 32-bit Reg ExtSel Memory Imm Ext ALU control MemWrt RegWrt 2 ALU enReg enImm enALU data data enMem Bus 32 rd M[(rs)] op (rt) Reg-Memory-src ALU op M[(rd)] (rs) op (rt) Reg-Memory-dst ALU op M[(rd)] M[(rs)] op M[(rt)] Mem-Mem ALU op 1/29/2009 CS152-Spring’09 CS252 S05
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Mem-Mem ALU Instructions: MIPS-Controller-2
Mem-Mem ALU op M[(rd)] M[(rs)] op M[(rt)] ALUMM0 MA Reg[rs] next ALUMM1 A Memory spin ALUMM2 MA Reg[rt] next ALUMM3 B Memory spin ALUMM4 MA Reg[rd] next ALUMM5 Memory func(A,B) spin ALUMM6 fetch Complex instructions usually do not require datapath modifications in a microprogrammed implementation -- only extra space for the control program Implementing these instructions using a hardwired controller is difficult without datapath modifications 1/29/2009 CS152-Spring’09 CS252 S05
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Performance Issues Microprogrammed control
multiple cycles per instruction Cycle time ? tC > max(treg-reg, tALU, tROM) Suppose 10 * tROM < tRAM Good performance, relative to a single-cycle hardwired implementation, can be achieved even with a CPI of 10 1/29/2009 CS152-Spring’09 CS252 S05
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Horizontal vs Vertical mCode
Bits per mInstruction # mInstructions Horizontal mcode has wider minstructions Multiple parallel operations per minstruction Fewer steps per macroinstruction Sparser encoding more bits Vertical mcode has narrower minstructions Typically a single datapath operation per minstruction separate minstruction for branches More steps to per macroinstruction More compact less bits Nanocoding Tries to combine best of horizontal and vertical mcode 1/29/2009 CS152-Spring’09 CS252 S05
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Nanocoding Exploits recurring control signal patterns in mcode, e.g.,
ALU0 A Reg[rs] ... ALUi0 A Reg[rs] mcode next-state PC (state) maddress mcode ROM nanoaddress nanoinstruction ROM data MC68000 had 17-bit mcode containing either 10-bit mjump or 9-bit nanoinstruction pointer Nanoinstructions were 68 bits wide, decoded to give 196 control signals 1/29/2009 CS152-Spring’09 CS252 S05
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Microprogramming in IBM 360
Datapath width (bits) 8 16 32 64 minst width (bits) 50 52 85 87 mcode size (K µinsts) 4 2.75 mstore technology CCROS TCROS BCROS mstore cycle (ns) 750 625 500 200 memory cycle (ns) 1500 2500 2000 Rental fee ($K/month) 7 15 35 Only the fastest models (75 and 95) were hardwired 1/29/2009 CS152-Spring’09 CS252 S05
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(650 simulated on 1401 emulated on 360)
Microcode Emulation IBM initially miscalculated the importance of software compatibility with earlier models when introducing the 360 series Honeywell stole some IBM 1401 customers by offering translation software (“Liberator”) for Honeywell H200 series machine IBM retaliated with optional additional microcode for 360 series that could emulate IBM 1401 ISA, later extended for IBM 7000 series one popular program on 1401 was a 650 simulator, so some customers ran many 650 programs on emulated 1401s (650 simulated on 1401 emulated on 360) 1/29/2009 CS152-Spring’09 CS252 S05
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Microprogramming thrived in the Seventies
Significantly faster ROMs than magnetic core memory or DRAMs were available For complex instruction sets (CISC), datapath and controller were cheaper and simpler New instructions , e.g., floating point, could be supported without datapath modifications Fixing bugs in the controller was easier ISA compatibility across various models could be achieved easily and cheaply Except for the cheapest and fastest machines, all computers were microprogrammed 1/29/2009 CS152-Spring’09 CS252 S05
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Writable Control Store (WCS)
Implement control store in RAM not ROM MOS SRAM memories now became almost as fast as control store (core memories/DRAMs were 2-10x slower) Bug-free microprograms difficult to write User-WCS provided as option on several minicomputers Allowed users to change microcode for each processor User-WCS failed Little or no programming tools support Difficult to fit software into small space Microcode control tailored to original ISA, less useful for others Large WCS part of processor state - expensive context switches Protection difficult if user can change microcode Virtual memory required restartable microcode 1/29/2009 CS152-Spring’09 CS252 S05
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Microprogramming: early Eighties
Evolution bred more complex micro-machines Ever more complex CISC ISAs led to need for subroutine and call stacks in µcode Need for fixing bugs in control programs was in conflict with read-only nature of µROM --> WCS (B1700, QMachine, Intel i432, …) With the advent of VLSI technology assumptions about ROM & RAM speed became invalid Better compilers made complex instructions less important Use of numerous micro-architectural innovations, e.g., pipelining, caches and buffers, made multiple-cycle execution of reg-reg instructions unattractive 1/29/2009 CS152-Spring’09 CS252 S05
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Microprogramming in Modern Usage
Microprogramming is far from extinct Played a crucial role in micros of the Eighties DEC uVAX, Motorola 68K series, Intel 386 and 486 Microcode pays an assisting role in most modern micros (AMD Athlon, Intel Core 2 Duo, IBM PowerPC) Most instructions are executed directly, i.e., with hard-wired control Infrequently-used and/or complicated instructions invoke the microcode engine Patchable microcode common for post-fabrication bug fixes, e.g. Intel Pentiums load µcode patches at bootup 1/29/2009 CS152-Spring’09 CS252 S05
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From CISC to RISC Use fast RAM to build fast instruction cache of user-visible instructions, not fixed hardware microroutines Can change contents of fast instruction memory to fit what application needs right now Use simple ISA to enable hardwired pipelined implementation Most compiled code only used a few of the available CISC instructions Simpler encoding allowed pipelined implementations Further benefit with integration In early ‘80s, could finally fit 32-bit datapath + small caches on a single chip No chip crossings in common case allows faster operation 1/29/2009 CS152-Spring’09 CS252 S05
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User PC Inst. Cache Hardwired Decode
Nanocoding User PC Exploits recurring control signal patterns in mcode, e.g., ALU0 A Reg[rs] ... ALUi0 A Reg[rs] mcode next-state PC (state) Inst. Cache maddress mcode ROM nanoaddress Hardwired Decode nanoinstruction ROM data MC68000 had 17-bit mcode containing either 10-bit mjump or 9-bit nanoinstruction pointer Nanoinstructions were 68 bits wide, decoded to give 196 control signals 1/29/2009 CS152-Spring’09 CS252 S05
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CDC 6600 Seymour Cray, 1964 A fast pipelined machine with 60-bit words
Ten functional units - Floating Point: adder, multiplier, divider - Integer: adder, multiplier ... Hardwired control (no microcoding) Dynamic scheduling of instructions using a scoreboard Ten Peripheral Processors for Input/Output - a fast time-shared 12-bit integer ALU Very fast clock, 10MHz Novel freon-based technology for cooling 1/29/2009 CS152-Spring’09 CS252 S05
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CDC 6600: Datapath Operand Regs 8 x 60-bit operand 10 Functional Units
result Central Memory 128K words, 32 banks, 1ms cycle IR Address Regs Index Regs 8 x 18-bit x 18-bit Inst. Stack 8 x 60-bit operand addr result addr 1/29/2009 CS152-Spring’09 CS252 S05
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CDC 6600: A Load/Store Architecture
Separate instructions to manipulate three types of reg. 8 60-bit data registers (X) 8 18-bit address registers (A) 18-bit index registers (B) All arithmetic and logic instructions are reg-to-reg Only Load and Store instructions refer to memory! Touching address registers 1 to 5 initiates a load 6 to 7 initiates a store - very useful for vector operations opcode i j k Ri (Rj) op (Rk) opcode i j disp Ri M[(Rj) + disp] 1/29/2009 CS152-Spring’09 CS252 S05
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CDC6600: Vector Addition B0 - n loop: JZE B0, exit
A0 B0 + a0 load X0 A1 B0 + b0 load X1 X6 X0 + X1 A6 B0 + c0 store X6 B0 B0 + 1 jump loop Ai = address register Bi = index register Xi = data register 1/29/2009 CS152-Spring’09 CS252 S05
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CDC6600 ISA designed to simplify high-performance implementation
Use of three-address, register-register ALU instructions simplifies pipelined implementation No implicit dependencies between inputs and outputs Decoupling setting of address register (Ar) from retrieving value from data register (Xr) simplifies providing multiple outstanding memory accesses Software can schedule load of address register before use of value Can interleave independent instructions inbetween CDC6600 has multiple parallel but unpipelined functional units E.g., 2 separate multipliers Follow-on machine CDC7600 used pipelined functional units Foreshadows later RISC designs 1/29/2009 CS152-Spring’09 CS252 S05
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“Iron Law” of Processor Performance
Time = Instructions Cycles Time Program Program * Instruction * Cycle Instructions per program depends on source code, compiler technology, and ISA Cycles per instructions (CPI) depends upon the ISA and the microarchitecture Time per cycle depends upon the microarchitecture and the base technology Microarchitecture CPI cycle time Microcoded >1 short Single-cycle unpipelined 1 long Pipelined this lecture 1/29/2009 CS152-Spring’09 CS252 S05
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CS152 Administrivia Check web site for new calendar, quiz dates should not change Feb 17 and Mar 17 lecture in 320 Soda All other lectures in 306 Soda (here) PS1 and Lab 1 available now or tomorrow PS 1 / Lab 1 due Tuesday February 10 Section tomorrow (Friday 1/30) 12-1pm 258 Dwinelle Covers lab 1 details Quiz 1 on Thursday Feb 12 1/29/2009 CS152-Spring’09 CS252 S05
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Hardware Elements Combinational circuits . .
Mux, Decoder, ALU, ... OpSelect - Add, Sub, ... - And, Or, Xor, Not, ... - GT, LT, EQ, Zero, ... Result Comp? A B ALU Sel O A0 A1 An-1 Mux . lg(n) A Decoder . O0 O1 On-1 lg(n) Synchronous state elements Flipflop, Register, Register file, SRAM, DRAM Clk D Q En ff Edge-triggered: Data is sampled at the rising edge 1/29/2009 CS152-Spring’09 CS252 S05
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Register Files ... register ff Register file 2R+1W
Q0 D0 Clk En Q1 D1 Q2 D2 Qn-1 Dn-1 ... register ReadData1 ReadSel1 ReadSel2 WriteSel Register file 2R+1W ReadData2 WriteData WE Clock rd1 rs1 rs2 ws wd rd2 we Reads are combinational 1/29/2009 CS152-Spring’09 CS252 S05
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Register File Implementation
rs1 ws clk wd rd1 rd2 rs2 5 32 32 32 5 5 reg 0 we reg 1 … … … reg 31 Register files with a large number of ports are difficult to design Almost all MIPS instructions have exactly 2 register source operands Intel’s Itanium, GPR File has 128 registers with 8 read ports and 4 write ports!!! 1/29/2009 CS152-Spring’09 CS252 S05
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A Simple Memory Model MAGIC RAM
ReadData WriteData Address WriteEnable Clock Reads and writes are always completed in one cycle a Read can be done any time (i.e. combinational) a Write is performed at the rising clock edge if it is enabled the write address and data must be stable at the clock edge Later in the course we will present a more realistic model of memory 1/29/2009 CS152-Spring’09 CS252 S05
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Implementing MIPS: Single-cycle per instruction datapath & control logic (Should be review of CS61C)
1/29/2009 CS152-Spring’09 CS252 S05
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The MIPS ISA Processor State Data types
32 32-bit GPRs, R0 always contains a 0 32 single precision FPRs, may also be viewed as 16 double precision FPRs FP status register, used for FP compares & exceptions PC, the program counter some other special registers Data types 8-bit byte, 16-bit half word 32-bit word for integers 32-bit word for single precision floating point 64-bit word for double precision floating point Load/Store style instruction set data addressing modes- immediate & indexed branch addressing modes- PC relative & register indirect Byte addressable memory- big endian mode All instructions are 32 bits 1/29/2009 CS152-Spring’09 CS252 S05
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Instruction Execution
Execution of an instruction involves 1. instruction fetch 2. decode and register fetch 3. ALU operation 4. memory operation (optional) 5. write back and the computation of the address of the next instruction 1/29/2009 CS152-Spring’09 CS252 S05
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Datapath: Reg-Reg ALU Instructions
0x4 Add clk addr inst Inst. Memory PC inst<25:21> inst<20:16> inst<15:11> inst<5:0> OpCode z ALU Control RegWrite clk rd1 GPRs rs1 rs2 ws wd rd2 we RegWrite Timing? 0 rs rt rd func rd (rs) func (rt) 1/29/2009 CS152-Spring’09 CS252 S05
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Datapath: Reg-Imm ALU Instructions
OpCode 0x4 Add clk addr inst Inst. Memory PC z ALU RegWrite rd1 GPRs rs1 rs2 ws wd rd2 we inst<25:21> inst<20:16> inst<31:26> Control Imm Ext ExtSel inst<15:0> opcode rs rt immediate rt (rs) op immediate 1/29/2009 CS152-Spring’09 CS252 S05
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Conflicts in Merging Datapath
RegWrite Introduce muxes 0x4 clk rd1 GPRs rs1 rs2 ws wd rd2 we Add inst<25:21> addr inst Inst. Memory PC z ALU inst<20:16> inst<15:11> clk Imm Ext ExtSel inst<15:0> inst<31:26> ALU Control inst<5:0> OpCode opcode rs rt immediate rt (rs) op immediate 0 rs rt rd func rd (rs) func (rt) 1/29/2009 CS152-Spring’09 CS252 S05
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Datapath for ALU Instructions
RegWrite 0x4 clk rd1 GPRs rs1 rs2 ws wd rd2 we Add <25:21> addr inst Inst. Memory PC <20:16> z ALU <15:11> clk <15:0> Imm Ext <31:26>, <5:0> ALU Control OpCode RegDst rt / rd ExtSel OpSel BSrc Reg / Imm opcode rs rt immediate rt (rs) op immediate 0 rs rt rd func rd (rs) func (rt) 1/29/2009 CS152-Spring’09 CS252 S05
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Datapath for Memory Instructions
Should program and data memory be separate? Harvard style: separate (Aiken and Mark 1 influence) - read-only program memory read/write data memory Note: Somehow there must be a way to load the program memory Princeton style: the same (von Neumann’s influence) single read/write memory for program and data A Load or Store instruction requires accessing the memory more than once during its execution 1/29/2009 CS152-Spring’09 CS252 S05
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Load/Store Instructions:Harvard Datapath
RegDst BSrc “base” disp ExtSel OpCode OpSel ALU Control z 0x4 Add clk addr inst Inst. Memory PC RegWrite rd1 GPRs rs1 rs2 ws wd rd2 we Imm Ext clk MemWrite addr wdata rdata Data Memory we WBSrc ALU / Mem addressing mode opcode rs rt displacement (rs) + displacement rs is the base register rt is the destination of a Load or the source for a Store 1/29/2009 CS152-Spring’09 CS252 S05
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MIPS Control Instructions
Conditional (on GPR) PC-relative branch Unconditional register-indirect jumps Unconditional absolute jumps PC-relative branches add offset4 to PC+4 to calculate the target address (offset is in words): 128 KB range Absolute jumps append target4 to PC<31:28> to calculate the target address: 256 MB range jump-&-link stores PC+4 into the link register (R31) All Control Transfers are delayed by 1 instruction we will worry about the branch delay slot later opcode rs offset BEQZ, BNEZ opcode rs JR, JALR opcode target J, JAL 1/29/2009 CS152-Spring’09 CS252 S05
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Conditional Branches (BEQZ, BNEZ)
PCSrc Add br RegWrite clk WBSrc MemWrite addr wdata rdata Data Memory we pc+4 0x4 Add clk we rs1 clk addr inst Inst. Memory PC rs2 rd1 ALU ws wd rd2 GPRs z Imm Ext ALU Control OpCode RegDst ExtSel OpSel BSrc zero? 1/29/2009 CS152-Spring’09 CS252 S05
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Register-Indirect Jumps (JR)
PCSrc br RegWrite clk WBSrc MemWrite addr wdata rdata Data Memory we rind pc+4 0x4 Add Add RegDst BSrc ExtSel OpCode z OpSel clk zero? addr inst Inst. Memory PC rd1 GPRs rs1 rs2 ws wd rd2 we Imm Ext ALU Control 1/29/2009 CS152-Spring’09 CS252 S05
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Register-Indirect Jump-&-Link (JALR)
PCSrc br RegWrite MemWrite WBSrc rind pc+4 0x4 Add Add RegDst BSrc ExtSel OpCode z OpSel clk zero? addr inst Inst. Memory PC rd1 GPRs rs1 rs2 ws wd rd2 we Imm Ext ALU Control clk 31 we addr rdata Data Memory wdata 1/29/2009 CS152-Spring’09 CS252 S05
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Absolute Jumps (J, JAL) Data Memory Inst. Memory GPRs 1/29/2009
PCSrc br RegWrite clk WBSrc MemWrite addr wdata rdata Data Memory we rind jabs pc+4 0x4 Add Add clk we rs1 clk addr inst Inst. Memory PC rs2 31 rd1 ALU ws wd rd2 GPRs z Imm Ext ALU Control OpCode RegDst ExtSel OpSel BSrc zero? 1/29/2009 CS152-Spring’09 CS252 S05
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Harvard-Style Datapath for MIPS
PCSrc br RegWrite clk WBSrc MemWrite addr wdata rdata Data Memory we rind jabs pc+4 0x4 Add Add RegDst BSrc ExtSel OpCode z OpSel clk zero? addr inst Inst. Memory PC rd1 GPRs rs1 rs2 ws wd rd2 we Imm Ext ALU Control 31 1/29/2009 CS152-Spring’09 CS252 S05
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Hardwired Control is pure Combinational Logic
ExtSel BSrc OpSel MemWrite WBSrc RegDst RegWrite PCSrc op code zero? 1/29/2009 CS152-Spring’09 CS252 S05
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ALU Control & Immediate Extension
Inst<5:0> (Func) Inst<31:26> (Opcode) ALUop + 0? OpSel ( Func, Op, +, 0? ) Decode Map ExtSel ( sExt16, uExt16, High16) 1/29/2009 CS152-Spring’09 CS252 S05
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Hardwired Control Table
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc ALU ALUi ALUiu LW SW BEQZz=0 BEQZz=1 J JAL JR JALR * Reg Func no yes ALU rd pc+4 sExt16 Imm Op pc+4 no yes ALU rt uExt16 pc+4 Imm Op no yes ALU rt sExt16 Imm + no yes Mem rt pc+4 pc+4 sExt16 Imm + yes no * sExt16 * 0? no * br sExt16 * 0? no pc+4 * no * jabs * no yes PC R31 jabs * no * rind * no yes rind PC R31 BSrc = Reg / Imm WBSrc = ALU / Mem / PC RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs 1/29/2009 CS152-Spring’09 CS252 S05
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Single-Cycle Hardwired Control: Harvard architecture
We will assume clock period is sufficiently long for all of the following steps to be “completed”: 1. instruction fetch 2. decode and register fetch 3. ALU operation 4. data fetch if required 5. register write-back setup time tC > tIFetch + tRFetch + tALU+ tDMem+ tRWB At the rising edge of the following clock, the PC, the register file and the memory are updated 1/29/2009 CS152-Spring’09 CS252 S05
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An Ideal Pipeline All objects go through the same stages
1 2 3 4 All objects go through the same stages No sharing of resources between any two stages Propagation delay through all pipeline stages is equal The scheduling of an object entering the pipeline is not affected by the objects in other stages These conditions generally hold for industrial assembly lines. But can an instruction pipeline satisfy the last condition? 1/29/2009 CS152-Spring’09 CS252 S05
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Pipelined MIPS To pipeline MIPS:
First build MIPS without pipelining with CPI=1 Next, add pipeline registers to reduce cycle time while maintaining CPI=1 1/29/2009 CS152-Spring’09 CS252 S05
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Pipelined Datapath write -back phase fetch execute decode & Reg-fetch
IR PC Add we rs1 rs2 rd1 addr we rdata ws addr wd ALU rd2 GPRs rdata Data Memory Inst. Memory Imm Ext wdata write -back phase fetch execute decode & Reg-fetch memory Clock period can be reduced by dividing the execution of an instruction into multiple cycles tC > max {tIM, tRF, tALU, tDM, tRW} ( = tDM probably) However, CPI will increase unless instructions are pipelined 1/29/2009 CS152-Spring’09 CS252 S05
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How to divide the datapath into stages
Suppose memory is significantly slower than other stages. In particular, suppose Since the slowest stage determines the clock, it may be possible to combine some stages without any loss of performance tIM = 10 units tDM tALU = 5 units tRF = 1 unit tRW 1/29/2009 CS152-Spring’09 CS252 S05
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Alternative Pipelining
0x4 IR PC Add we rs1 rs2 rd1 addr we rdata ws addr wd ALU rd2 GPRs rdata Data Memory Inst. Memory Imm Ext wdata write -back phase fetch execute decode & Reg-fetch memory tC > max {tIM, tRF, tALU, tDM, tRW} = tDM tC > max {tIM, tRF+tALU, tDM, tRW} = tDM tC > max {tIM, tRF+tALU, tDM+tRW} = tDM+ tRW increase the critical path by 10% Write-back stage takes much less time than other stages. Suppose we combined it with the memory phase 1/29/2009 CS152-Spring’09 CS252 S05
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Summary Microcoding became less attractive as gap between RAM and ROM speeds reduced Complex instruction sets difficult to pipeline, so difficult to increase performance as gate count grew Iron Law explains architecture design space Trade instruction/program, cycles/instruction, and time/cycle Load-Store RISC ISAs designed for efficient pipelined implementations Very similar to vertical microcode Inspired by earlier Cray machines MIPS ISA will be used in class and problems, SPARC in lab (two very similar ISAs) 1/29/2009 CS152-Spring’09 CS252 S05
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Acknowledgements These slides contain material developed and copyright by: Arvind (MIT) Krste Asanovic (MIT/UCB) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Patterson (UCB) MIT material derived from course 6.823 UCB material derived from course CS252 1/29/2009 CS152-Spring’09 CS252 S05
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