1. Project Block Diagram Transmitter Receiver × 2 Input Device Protection
Analog Channels from Receiver (Left & Right Rear)
Transmitter
Input Device
Protection
(Ayo)
ADC
(Ayo)
IR Transmitter
(Kevin)
Analog
Digital
Infrared
Receiver × 2
Amplifier
(Brian)
DAC
(Ayo)
IR Receiver
(Kevin)
Analog
Digital
Analog Channel to Speaker
Transmitter
Power Supply
(Eenas)
Receiver
Protection
(Rick & Brian)
Receiver
Power Supply
(Rick)
Ayodeji Opadeyi Team #2

2. ADC Schematic
Ayodeji Opadeyi Team #2

3. ADC Device Packaging Prototype Product Thru Hole Surface mount
Ayodeji Opadeyi Team #2

4. ADC Components Prototype
eight 5% tolerance resistors, ½ W (R1 = 3.9kΩ, R2 = 10kΩ, R5 = 3kΩ)
Two clock circuits
two op-amps
four diodes, ½ W
Four 10µF 20% tolerance capacitors,
Eight 0.1µF 20% tolerance capacitors
2 Max195 chips (DIP)
Product
Eight 5% tolerance resistors, ½ W (R1 = 3.9kΩ, R2 = 10kΩ, R5 = 3kΩ)
Four 10µF 20% tolerance capacitors
2 Max195 chips (Surface mount)
Ayodeji Opadeyi Team #2

5. ADC Resistor Selection
R1 = 10 kΩ
R2 = 3.9 kΩ
R5 = R1 || R2 = 3k Ω
R7 = 100 Ω
When choosing the above resistors, the noise was considered:
vn2 = 4kTRB
From the above equation we see that when the resistor is increased, the square of the noise voltage also increases.
The current entering the ADC also has to be minimized, therefore I chose resistors appropriately.
With the above considerations in mind, I chose my resistor values in order to have the ADC input current at its minimum, and the noise voltage at its minimum.
Ayodeji Opadeyi Team #2

6. ADC Design Calculation
Maximum Voltage Output from Audio Receiver: 8Vrms
Maximum Input Analog Voltage to ADC: 4.75Vrms
Maximum Gain Signal Conditioner Allowed: 0.594
Ayodeji Opadeyi Team #2

7. Gain Error due to Resistor Tolerances
Ayodeji Opadeyi Team #2

8. Gain Error (Continued)
Ayodeji Opadeyi Team #2

9. Input Offset Voltage Error
Ayodeji Opadeyi Team #2

10. Input Offset/Bias Current Error
Ayodeji Opadeyi Team #2

11. Gain Error
Ayodeji Opadeyi Team #2

12. Gain Error (Continued)
Ayodeji Opadeyi Team #2

13. ADC Prototype Bill Of Materials
Component
Unit Price
Qty
Price
Resistor (5%)
$0.046 8
$0.368
Clock circuit
$5.00 2
$10.00
Op-amp
$3.55
$7.10
Diode
$0.10 4
$0.40
10µF Capacitor (20%) $
$1.409
0.1µF Capacitor (20%)
$0.20
$1.60
ADC Max195 chip (DIP)
$2.56
$5.12
Total
$25.997
Ayodeji Opadeyi Team #2

14. ADC Product Bill Of Materials
Component
Unit Price
Qty
Price
Manufacturer
Package
Resistor (5%)
$0.046 8
$0.368
OHMITE
Axial Leaded
Clock circuit
$5.00 2
$10.00
N/A
DIP
Op-amp
$3.55
$7.10
MAXIM-IC
Diode
$0.10 4
$0.40
FAIRCHILD SEMICONDUCTORS
10µF Capacitor (10%) $
$1.409
BC COMPONENTS
0.1µF Capacitor (10%)
$0.20
$1.60
NICHICON
ADC Max195 chip
$2.56
$5.12
Total
$25.997
Ayodeji Opadeyi Team #2

15. ADC Analog Block DFM Plan
Sub Circuit
Type
Applicable Worst Case Analysis Plan
(See DFM Analysis Guide)
Task 1
Task 2
Task 3
Task 4
Task 5
Task 6
Task 7
Task 8
Task 9
Task 10
16 Bit A-D Converter
R, L & C Tol
RLC Specs
Max Offset
Error
Max
Gain
Max DNL
Max INL
Input
Impedance
Worst Case Total Error
Bits, Volts
Sample/
Hold Required?
Conversion Speed
Signal Conditioning
Fn(s)
Ayodeji Opadeyi Team #2

16. ADC Digital Block DFM - DC Drive Analysis Table
Device
Output
Type
Input Type
Tech Type
DC Drive Device Parameters
Vil
max
Vih
min
Iil (-)
Max
Iih
Vol
Voh
Iol
Ioh (-)
Min
Vhyst
Checked
16 Bit A-D Converter
STD
CMOS
N/A
0.4V
3.5V
250uA
-250uA
Ayodeji Opadeyi Team #2

17. ADC Digital Block DFM - Timing Analysis Table
Dig Signal
Output
Type
Input Type
Timing Parameters
Other
Tsu
Setup Th
Thold
Marg
Fmax F
Tpulse
Min
Checked
Serial output digital
Std
80 ns
40ns
25ns
35ns
1.7MHz
120ns
Ayodeji Opadeyi Team #2

18. System Level Block Diagram
Analog Channels from Receiver (Left & Right Rear)
Transmitter
Input Device
Protection
( Ayo)
ADC
(Ayo)
IR Transmitter
(Kevin)
Analog
Digital
Infrared
Receiver × 2
Amplifier
(Brian)
DAC
(Ayo)
IR Receiver
(Kevin)
Analog
Digital
Analog Channel to Speaker
Transmitter
Power Supply
(Eenas)
Receiver
Protection
(Rick & Brian)
Receiver
Power Supply
(Rick)
Ayodeji Opadeyi Team #2

19. DAC Schematic
Ayodeji Opadeyi Team #2

20. DAC Device Packaging Prototype Product Thru Hole Surface mount
Ayodeji Opadeyi Team #2

21. DAC Components Prototype eight 5% resistors Two clock circuits
two op-amps
Four 20% 10µF capacitors
Eight 20% 0.1µF capacitors
2 Max541 chips (DIP)
Product
2 Max541 chips (Surface mount)
Ayodeji Opadeyi Team #2

22. DAC Resistor Selection
R1 = 10 kΩ
R2 = 3.9 kΩ
R5 = R1 || R2 = 3k Ω
R7 = 10 Ω
R7 was chosen because the data sheet specified it, the other resistors were chosen in order to revert the signal, so I just swapped the ADC resistors.
Ayodeji Opadeyi Team #2

23. Gain Error due to Resistor Tolerances
Ayodeji Opadeyi Team #2

24. Input Offset Voltage Error
Ayodeji Opadeyi Team #2

25. Input Offset/Bias Current Error
Ayodeji Opadeyi Team #2

26. Gain Error
Ayodeji Opadeyi Team #2

27. Gain Error (Continued)
Ayodeji Opadeyi Team #2

28. DAC Prototype Bill Of Materials
Component
Unit Price
Qty
Price
Resistor (5%)
$0.046 8
$0.368
Clock circuit
$5.00 2
$10.00
Op-amp
$3.55
$7.10
10µF Capacitor (20%) $ 4
$1.409
0.1µF Capacitor (20%)
$0.20
$1.60
DAC Max541 chip (DIP)
$2.56
$5.12
Total
$25.597
Ayodeji Opadeyi Team #2

29. DAC Product Bill Of Materials
Component
Unit Price
Qty
Price
Manufacturer
Package
Resistor (5%)
$0.046 8
$0.368
OHMITE
Axial Leaded
Clock circuit
$5.00 2
$10.00
N/A
DIP
Op-amp
$3.55
$7.10
MAXIM-IC
10µF Capacitor (20%) $ 4
$1.409
BC COMPONENTS
0.1µF Capacitor (20%)
$0.20
$1.60
NICHICON
DAC Max541 chip
$2.56
$5.12
Total
$25.597
Ayodeji Opadeyi Team #2

30. DAC Analog Block DFM Plan
Sub Circuit
Type
Applicable Worst Case Analysis Plan
(See DFM Analysis Guide)
Task 1
Task 2
Task 3
Task 4
Task 5
Task 6
Task 7
Task 8
Task 9
Task 10
16 Bit D-A Converter
V or I transfer Function
Max Offset Voltage
DC Gain vs Component Variations
Gain vs Freq vs Comp Variation
Pulse Response and Delay
Output Impedance
Noise and/or Ripple
Semiconductor Power & Junct Temps
Semiconductor Package & Heatsink
Signal Restoration
R, L & C Tol
RLC Specs
Max Offset
Error
Max
Gain
Max DNL
Max INL
Input
Impedance
Fn(s)
Ayodeji Opadeyi Team #2

31. DAC Digital Block DFM - DC Drive Analysis Table
Device
Output
Type
Input Type
Tech Type
DC Drive Device Parameters
Vil
max
Vih
min
Iil (-)
Max
Iih
Vol
Voh
Iol
Ioh (-)
Min
Vhyst
Checked
D-A Converter
STD
CMOS
1.5V
3.5V
10uA
-10uA
N/A
Ayodeji Opadeyi Team #2

32. DAC Digital Block DFM - Timing Analysis Table
Dig Signal
Output
Type
Input Type
Timing Parameters
Other
Tsu
Setup Th
Thold
Marg
Fmax F
Tpulse
Min
Checked
Serial Input
Std
40ns
0ns
5ns
45ns
10MHz
Std = Standard, OC = Open Collector/Drain, TS = Tristate, ST – Schmitt Trigger
Ayodeji Opadeyi Team #2