1. Analog-to-Digital and Digital-to-Analog Conversion
Introduction (Applications and S/H Circuit)
DAC
ADC
Conversion between analog and digital signals is common. The following aspects will be examined:
Properly sampling of analog signals by a Sample and Hold (S/H) circuit composed of a LF398 IC
D/A conversion and A/D conversion principles
Different conversion methods (different circuit implementations)
DAC0808 and ADC0804 used in the Practicum assignment
Digital quantities – values can take on one of two possible values. Actual values can be in a specified range so the exact value is not important.
Analog quantities – values can take on an infinite number of values, and the exact value is important.
ECE M. A. Jupina, VU, 2014

2. Computerized Motor Control Through the Use of a DAC
For an 8-bit DAC, when the digital input is or FF or 255 then the full-scale output current (IOUT) is 2mA. This current is then amplified to drive the motor at 1000 rpm (revolutions per minute).
ECE M. A. Jupina, VU, 2014

3. Example: Function Generator Using a ROM and a DAC
Low Pass
Filter
TSIGNAL
TCLK
Synthesized Source Example
Counter counts from 0 to 255 (N = number of bits = 8). Counter selects a particular 8-bit word location in the ROM at each count. DAC (Digital-to-Analog Converter) converts the digital signal (8 bit word) into an analog voltage signal between 0 and (255/256) Vref (reference voltage of the DAC).
8-bit resolution: If Vref = 5V, then Voltage resolution of DAC = DeltaV=5/28=19.5 mV
Output signal can vary between 0 and 4.98V for Vref = 5V so Voutpp = 4.98V.
256 values per cycle: TSIG = 256 TCLK, fSIG = fCLK/256
RC Circuit: Low pass filter to remove the higher frequency quantization effect in the signal (the “steps” in the sinusoidal signal)
ECE M. A. Jupina, VU, 2014

4. What clock frequency will result in a 100 Hz sine wave at the output?
What method could be used to vary the peak-to-peak amplitude of the sine wave?
Adjust the reference voltage of the DAC.
ECE M. A. Jupina, VU, 2014

5. Programmable Gain Amplifier with a DAC
AC Input Signal
DC Input Signal
Digital
Inputs IO
AC Output Signal
Both a DC and an AC “reference” voltage used as an analog input
A = amplification factor = 0 to 255 for an 8-bit DAC
OP AMP Review:
Since the non-inverting input (node 3 of LF351) is at ground, the inverting input (node 2) is at 0V.
Since the input currents at the non-inverting and inverting nodes are zero, the current, IO, entering node 2 is equal to the current entering node 4 of the DAC0808.
DC Blocking Capacitor – only time-varying voltages pass through. IO
DC Blocking Capacitor
ECE M. A. Jupina, VU, 2014

6. DVM Using an ADC
Continuous-conversion DVM (digital volt meter) using a digital-ramp ADC. A DAC is actually part of this ADC.
BCD counters start to count when triggered by the reset signal from Q2. BCD counters are used as inputs to a DAC.
A voltage comparator compares the analog voltage, VAX, generated by the DAC (BCD-to-A converter) with the input analog voltage, VA.
Once VAX > VA, then the comparator’s output goes LOW and the count value of the BCD counters is stored in the 4-bit registers. 7-segment decoders display these 4-bit values on the 7 segment displays.
ECE M. A. Jupina, VU, 2014

7. Real World Applications
Analog-to-digital converters (ADC) and digital-to-analog converters (DAC) are used to interface a computer to the analog world so that the computer can monitor and control a physical variable.
ECE M. A. Jupina, VU, 2014

8. Data Sampling System Block Diagram
Anti-Alias filter (low pass filter) blocks high frequency signals that would generate an “alias” signal at the output (more about this later).
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9. Simplified Diagram of a Sample-and-Hold Circuit
When an analog voltage is connected directly to the input of an ADC, the conversion process can be adversely affected if the analog voltage is changing during the conversion time. The stability of the conversion process can be improved by using a sample-and-hold circuit to hold the analog voltage constant while the A/D conversion is taking place.
A1 and A2 – unity gain amplifiers (“voltage followers” with high input impedance and low output impedance)
Ch – hold capacitor which stores the analog input voltage
Digitally controlled switch – closed during the sample mode and open during the hold mode
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10. LF398 Sample-and-Hold (S/H) Circuit
The internal block diagram of the LF398 is shown above as wired in a typical S/H circuit.
When the S/H is in the "sample" state, with the control voltage above 1.4 V, the voltage at the input appears at the output, and varies simultaneously. A S/H presents a very high input impedance, and its bandwidth is considerable. When the control is changed to "hold," below 1.4 V, the sampled voltage is held on a hold capacitor and the output voltage is frozen at that point. There is a settling time after the hold command until the output is within 1 mV of its steady value. For the LF398, this is about 0.8 μs. After the hold command, the aperture time is the time after which changes of the input voltage no longer affect the output voltage. For the LF398, it is ns. The acquisition time is the time for the internal nodes to settle, and the output to be within, say, 0.1% of its final value. The acquisition time depends on the size of the hold capacitor. For the LF398, with a 0.01 μF hold capacitor, it is about 20 μs. Times for the hold command are measured from the 1.4 V point of the control waveform.
Even if the times are taken into account, the accuracy of the output depends on several more parameters. First, the S/H acts like a unity-gain buffer, and its gain may vary slightly from 1. This gain error is less than 0.01% maximum at 25°C. Secondly, there is a finite jump in the output voltage called the hold step when the hold command is issued. For a hold capacitor of 0.01 μF, this is 0.5 mV typically, 2.5 mV maximum for the LF398. Finally, there is droop as the hold capacitor voltage declines steadily in the "hold" state. This droop is caused mainly by a constant leakage current, and can be predicted fairly well, so that corrections can be made for it if desired. All of this should convince you that it is a challenging task to design a good S/H circuit.
Selection of the hold capacitor is an important matter. The larger the hold capacitance, the smaller is the droop. The smaller the hold capacitor, the more quickly it can be charged and the smaller the acquisition time. There is, therefore, a tradeoff in selection of hold capacitor size. For most normal uses, a value of 0.01 μF is satisfactory, and values in the range 1 nF to 1 μF are usual. The type of capacitor used is important. It is obvious that the capacitor should have small leakage, so all electrolytics, whether aluminum or tantalum, are excluded. The next most important characteristic is "dielectric absorption" or hysteresis in the dielectric constant. This means that the voltage is not a single valued function of the charge on the capacitor, as it should be for a S/H circuit. The capacitor voltage changes as the dielectric "relaxes,“ as well as when charge is supplied or taken away. Ceramic capacitors are unusable because of their high hysteresis, greater than 1% of the voltage on them. Otherwise excellent mica and polycarbonate capacitors have less hysteresis, but still too much for a S/H. The three dielectrics that are suitable for an accurate S/H circuit are polypropylene, polystyrene and Teflon, roughly in that order. Polypropylene has the least hysteresis of all, and is the best choice for a hold capacitor, but any of the three will give adequate results. mF
ECE M. A. Jupina, VU, 2014

11. Block Diagram of a Digital Storage Oscilloscope
Makes use of D/A and A/D converters
ADC samples the analog input, the digital value is stored, and DACs are used to generate voltages that point the electron beam in the CRT to the X-Y location on the scope screen.
Some advantages of the digital scopes over analog scopes:
Waveform storage
Stored waveform display for comparison
Waveform parameter extraction (amplitudes, periods, frequencies, etc)
Store and display waveforms before the trigger point
Print waveforms or transfer data to a PC
ECE M. A. Jupina, VU, 2014

12. Digital Signal Processor (DSP) Architecture
Specialized microprocessor optimized for repetitive calculations on streams of digitized data
DSP is used frequently in filtering and conditioning of analog signals
- Perform the same function as analog filters but allow greater flexibility
- Can perform dynamic frequency adjustment
DSP concepts involve: ADC and DAC, data acquisition, sampling, signed binary numbers, signed binary addition and multiplication, and shift registers
DSP applications:
Filters in CD players to minimize quantization noise
Echo canceling in telephone systems
PC modems
Musical instrument special effects
Digital television
Voice recognition
DSP continues to grow into almost all electronic systems
ECE M. A. Jupina, VU, 2014

13. Digital Filter (FIR Low Pass) Implementation on UP1 Board
Ideal FIR LP Filter
An example of a previous project using discrete components.
Ideal FIR LP filter (Order = infinity)
Frequencies below 2500 Hz are passed and frequencies above 2500 Hz are blocked (or attenuated).
Not practical to implement – too large of a circuit on a chip.
A finite impulse response (FIR) low pass filter with a cutoff frequency of 2500 Hz will be implemented in the latter sections of part III of the DAC and ADC practicum. The UP 1 board will be programmed to implement the filter design. The UP 1 board will be placed between the 8 digital output pins of the ADC0804 and the 8 digital input pins of the DAC0808.
The FIR low pass filter is designed by running the MATLAB firlp_8.m script file. The coefficients for a 2500 Hz low pass filter are generated by this script file. The order of the filter is 8. Bode plots (normalized gain, Vout/Vin, and phase, PHIout- PHIin, versus frequency) of this filter are generated by another script file.
Using the filter coefficient’s calculated in MATLAB, VHDL implementation of the FIR low pass filter is performed by an integer processor with shift-and-add operations.
Scope measurements on the FIR filter are performed and compared to the Bode plot results.
ECE M. A. Jupina, VU, 2014

14. Example Filter Measurements on a Scope
ALL Pass Filter (Sampling Effects)
ALL Pass Filter (Alias Signal)
FIR Low Pass Filter (Gain and Phase Measurements)
Vinpp
The top signals in each scope screen are the input signals to the ADC (channel 1). The bottom signals in each scope screen are the output signals from the DAC (channel 2).
Before measurements on the FIR LP filter, measurements are performed on an ALL PASS filter (digital signals from the output of the ADC are directly passed to the digital inputs of the DAC). Thereby, the effects of sampling in an ADC-DAC system are observed.
Top left scope screen shows how the output signal becomes quantized after passing through an ADC-DAC system.
Top right scope screen shows an Alias output signal since the input signal frequency exceeds the maximum frequency set by the Nyquist condition.
The bottom scope screen shows a measurement on the FIR LP filter. The output signal lags the input signal since the phase shift is negative. T is the period of the signals.
Voutpp Df
ECE M. A. Jupina, VU, 2014

15. Digital-to-Analog Conversion
Definitions
Example Problems
Various DAC Circuitries
DAC0808
The conversion process:
Digital code is converted to a proportional voltage or current
Reference voltage determines the max output DAC can output
Analog (pseudo analog) output – only certain analog values are available depending on the resolution
DAC Applications:
Control - Use a digital computer output to adjust motor speed or furnace temperature
Automatic testing - Computer generated signals to test analog circuitry
Signal reconstruction - Restoring an analog signal after it has been converted to digital. Audio CD systems, and audio/video recording
A/D conversion
ECE M. A. Jupina, VU, 2014

16. Four-Bit DAC with Voltage Output
VREF = 16 V
Full Scale or Maximum Voltage: VFS = 15 V
Reference Voltage: VREF = 16V
Number of bits: N=4
Resolution or Step Size: VSTEP = 1V (defined in terms of either the reference or full scale value)
ECE M. A. Jupina, VU, 2014

17. Output Waveform of a 4-Bit DAC with a Binary Counter Supplying the Input
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18. DAC Transfer Function
For N = finite number, the transfer function is a staircase.
As N goes to infinity (step size goes to zero), the transfer function becomes linear. Therefore, every possible analog voltage is generated over a certain range.
ECE M. A. Jupina, VU, 2014

19. Definitions where N is number of bits
Full Scale Output – the maximum value that the D/A converter can produce.
Resolution or Step Size – the smallest change that can occur in the analog output as a result of a change in the digital input.
where N is number of bits
Analog Output = K • decimal value of the digital input
Percentage Resolution
Accuracy
Full Scale Error – maximum deviation of the DAC’s output from its ideal value.
Linearity Error – maximum deviation in step size from the ideal step size.
Offset Error – the small output voltage that exists when all inputs are “0”
Settling Time – the time required for the DAC output to go from zero to full scale as the binary input goes from all 0’s to all 1’s.
AFS – full scale output
Key specifications are:
Resolution
Accuracy
Offset error
Settling time
ECE M. A. Jupina, VU, 2014

20. Example Problems
An eight-bit DAC produces an output voltage of 2.0 V for an input code of What will the value of VOUT be for an input code of ?
= 10010
= 17910
(179/100) = (X/2V)
X = 3.58V
What is the resolution of the DAC in the previous? Express it in volts and as a percentage. Determine the weight of each input bit.
Resolution = 2V/100 = 20mV
Full Scale Voltage = 20mV (28 -1) = 5.1V
% Resolution = [20mV / {20mV (28 -1) }] x 100%  0.4%
LSB = 2V/100 = 20mV
Other bits: 40mV, 80mV, 160mV, 320mV, 640mV, 1280mV, and 2560mV.
ECE M. A. Jupina, VU, 2014

21. Example Problems
What is the resolution in volts of a 10-bit DAC whose Full-Scale output is 5 V?
10 bits---> = 1023 steps
Resolution = 5V/1023 = 4.89 mV  5mV
How many bits are required for a DAC so that its Full-Scale output is 10 mA and its resolution is less than 40 mA?
The maximum resolution is 40µA. The number of steps required to produce 10mA full scale will be at least 10mA/40µA = 250.
Therefore, it requires at least 8 bits.
ECE M. A. Jupina, VU, 2014

22. Example Problems
Assuming a 12-bit DAC with perfect accuracy, how close to 250 rpm can the
motor speed be adjusted for the motorized system below?
12-bit DAC gives us steps = Step-Size = 2mA/4095 = 488.4nA
To have exactly 250 RPM the output of the DAC must be
(250 RPM x 2mA) / 1000 RPM = 500µA.
In order to have 500µA at the output of the DAC, the computer must increment the input of the DAC to the count of 500µA/488.4nA =
Thus, the motor will rotate at (1024/4095) x 1000 RPM = RPM when the computer's output has incremented 1024 steps.
ECE M. A. Jupina, VU, 2014

23. Example Problems
An eight-bit DAC has a full-scale error of 0.2% F.S. If the DAC has a full-scale output of 10 mA, what is the most that it can be in error for any digital input? If the DAC output reads 50 mA for a digital input of , is this within the specified range of accuracy? (Assume no offset error.)
Full Scale error = 0.2% x 10mA = 20µA
Step-Size = 10mA/255 = 39.2µA. Ideal output for is 39.2µA.
The possible range is 39.2µA ± 20µA = 19.2µA to 59.2µA.
Thus, 50µA is within this range.
F.S. – full scale value
ECE M. A. Jupina, VU, 2014

24. Example Problems
A particular 6-bit DAC has a full-scale output rated at V. Its accuracy is specified as ± 0.1% F.S., and it has an offset error of ±1 mV. Assume that the offset error has not been zeroed out. Consider the measurements made on this DAC in the table below, and determine which of them are not within the device’s specifications.
Step-Size = 1.26V/63 = 20mV
±0.1% F.S. = ±1.26mV
Thus, maximum error will be
±1.26mV ±1mV = ±2.26 mV.
> 2 x 20mV = 40mV [41.5mV is within specs.] .
> 7 x 20mV = 140mV [140.2mV is within specs.] .
> 12 x 20mV = 240mV [242.5mV isn't within specs.] .
> 63 x 20mV = 1.260V [1.258 V is within specs.] .
Input Code
Output
000010
41.5 mV
000111
140.2 mV
001100
242.5 mV
111111
1.258 V
Total or max error here = full scale error + offset error
ECE M. A. Jupina, VU, 2014

25. Simple DAC Using an Op-Amp Summing Amplifier with Binary-Weighted Resistors
1 KW
1 KW
2 KW
4 KW
8 KW
A summing operational amplifier with a resolution of V
The output produces the weighted sum of the inputs.
Inputs A, B, C, and D – binary inputs that are assumed to have values of either 0 or 5V.
Superposition technique can be used to calculate VOUT.
Conversion accuracy is a problem here since a “1” state is usually not exactly 5V and a “0” state is usually not exactly 0V. Therefore, not a very accurate DAC.
ECE M. A. Jupina, VU, 2014

26. Improved DAC using Summing Amplifier with Precision Voltage Source
1 KW
2 KW
1 KW
4 KW
Precision reference supply implementation solves the conversion accuracy issue of the previous summing amplifier design.
Digital Inputs control switches (CMOS transmission gates) that are either on and the inputs are connected to a precision reference voltage or are off and the inputs are left floating (0 V input).
However, circuits with binary weighted resistors are still problematic due to the large difference in R values between the LSB and the MSB – IC fabrication issue
8 KW
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27. Basic R/2R Ladder DAC
The R/2R ladder uses resistances that span only a 2 to 1 range – easier to fabricate on an IC
B – input value which ranges from 0000 (0) to 1111 (15) for this example.
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28. DAC0808 R/2R Ladder DAC with Current Output
DAC used in the practicum assignment
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29. DAC0808 Block Diagram Refer to the data sheet for details.
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30. DAC0808 Specifications The DAC0808 is an 8-bit monolithic DAC
Full Scale Error: ±0.19%
Offset current levels less than 4 mA for
Maximum output current: 2 mA.
Fast settling time: 150 ns typical
Power supply voltage range: ±4.5V to ±18V
Low power consumption: 33 ±5V
ECE M. A. Jupina, VU, 2014

31. DAC Circuit
MSB
LSB
The DAC0808 has a bit resolution of 8 and operates with a maximum of +18 and –18 VDC. The DAC0808 has an internal R/2R ladder D/A converter. For the DAC0808 IC, the output is in terms of an output current, Io, instead of an output voltage. The full-scale output current (IFS) is the maximum output current when all the inputs are "1". An operational amplifier (op-amp) is used in the output stage of the circuit below to convert the output current into an output voltage (Eo). The op-amp also protects the D/A converter IC from load variations.
A values – binary values of 0 or 1. A1 is the MSB and A8 is the LSB.
Assuming matched resistors (RF = Rref), thus EO = Vref [A1/2 + A2/4+ … ].
For conversion accuracy, 1% tolerance resistors or better should be used.
ECE M. A. Jupina, VU, 2014

32. Analog-to-Digital Conversion
Definitions
Effects of Sampling
Various ADC Circuitries
Example Problems
ADC0804
ADC – digital code represents the analog input
Generally more complex circuitry and conversion times are much longer than a DAC (settling time)
Several types of ADCs use DAC circuits
ECE M. A. Jupina, VU, 2014

33. General Diagram of One Class of ADCs
The Op amp comparator ADC
Variations differ in how the control section continually modifies numbers in the register
A binary counter is used as the register and allows the clock to increment the counter a step at a time until VAX VA
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34. Typical Computer Data Acquisition System
Waveforms showing how the computer
initiates each new conversion cycle and
then loads the digital data into memory
at end of conversion (EOC).
Start (Data Request) and EOC (Data Ready) signals create a “full handshake.”
VA – analog input voltage
ECE M. A. Jupina, VU, 2014

35. ADC Ideal Linear Transfer Function
For N = finite number, the transfer function is a staircase.
As N goes to infinity (step size goes to zero), the transfer function becomes linear. Therefore, every possible analog input voltage over a certain range is represented by a binary number.
ECE M. A. Jupina, VU, 2014

36. Definitions where N is number of bits
Full Scale Input – the maximum value that the A/D converter can accept.
Resolution or Step Size – the smallest change that can occur in the analog input to produce a change in the digital output.
where N is number of bits
Accuracy
Quantization Error – the maximum difference between the actual analog input voltage and the digital output value representing it. This is equal to the resolution.
Full Scale Error – maximum deviation in the ADC’s comparator reference voltage or the internal DAC’s output voltage from the ideal value.
Conversion Time – the time required for the ADC to convert an analog input voltage into a digital output.
AFS – full scale input
Key specifications are:
Resolution
Accuracy
Conversion time
ECE M. A. Jupina, VU, 2014

37. Digitizing an Analog Signal
ADC
DAC
Analog input signal sampled at equal intervals (Δt).
“A/D output” signal shown is actually the analog output signal from a DAC (effects of sampling shown).
A Low pass filter is used to remove the higher frequency quantization effect in the signal (the “steps” in the signal) and thus the original signal is reconstructed.
LPF
fed through a DAC
ECE M. A. Jupina, VU, 2014

38. Nyquist Criterion
In order to avoid loss of information, the incoming signal must be sampled at a rate greater than two times the highest frequency component in the incoming signal.
Example: CD Audio, FSAMPLING = 44 KHz since FMAX = 22 KHz
A signal alias is produced by sampling the signal at a rate less than the minimum rate (twice the highest frequency).
Harry Nyquist
- The sampling frequency must be at least twice the highest input frequency
- Sampling at a frequency less than twice the input frequency results in under sampling and incorrect reproduction
At F=FMAX, Nyquist Criterion guarantees two sampling points per period or cycle.
Aliasing - Caused by under sampling
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39. An Alias Signal Due to Under-Sampling
Sine wave frequency is 1.9 KHz. This signal is sampled every 500 ms (FSAMPLING = 2 KHz). Data samples are indicated by square dots. These square dots form a sinusoidal waveform with a period of 10 ms or a frequency of 100 Hz.. The alias frequency is the difference between the sampling frequency and the frequency of the incoming signal.
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40. Digital-Ramp ADC Simplest conversion technique.
Conversion time is variable and dependent on the analog input (conversion time increases as analog input increases).
“Over-estimates” or “Rounds-up” the analog input value since VAX > VA when the digital output value is stored.
For example, for a 4-bit ADC with a resolution of 1 V, if VA = 11.2 V, then the count of 1100 (12) is stored when VAX reaches 12 V.
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41. Three-Bit Flash ADC A 3 bit flash converter is shown above
3 KW
1 KW
1 KW
1 KW
1 KW
1 KW
1 KW
1 KW
A 3 bit flash converter is shown above
Upside: High speed conversion
Conversion time – No clock signal is used, so the conversion is continuous. This makes for very short conversion times, typically under 17 ns (limited by the propagation delay of the signals through the chip).
Downside: large area circuits on a chip (therefore, there is a practical limit of fabricating Flash ADCs with more than 12 bits)
Much more complex circuitry (2N resistors and 2N-1 analog comparators)
6 bit flash ADC requires 63 analog comparators
8 bit flash ADC requires 255 comparators
10 bit flash ADC requires 1023 comparators
“Under-estimates” or “Rounds-down” the analog input value when the digital output value is generated by the priority encoder.
For example, if VA = 1.5V, then the digital output is 001.
ECE M. A. Jupina, VU, 2014

42. Four-Bit Successive-Approximation ADC
Widely used ADC
More complex than digital ramp but has a shorter conversion time
Conversion time is fixed and not dependent on the analog input
Many Successive Approximation ADCs are available as ICs.
Search tree approach implemented by control logic that modifies the contents of the register bit by bit (starting with the MSB) until the register’s data is the digital equivalent of the analog input voltage, VA, within the resolution of the converter. Flow chart demonstrating the control algorithm is shown above.
“Under-estimates” or “Rounds-down” the analog input value since VAX < VA when the digital output value is stored.
For example, for a 4-bit ADC with a resolution of 1 V, if VA = 11.2 V, then the count of 1011 (11) is stored when VAX reaches 11 V.
ECE M. A. Jupina, VU, 2014

43. Example Problems 6.005 V / 40 mV = 150.125 = 15110 = 100101112.
An eight-bit digital ramp ADC with a 40 mV resolution uses a clock frequency of 2.5 MHz. Determine the following values:
the digital output for an analog voltage of V
the digital output for an analog voltage of V
the maximum and average conversion times
6.005 V / 40 mV = = =
Using same method as in (a) the digital value is again
Maximum conversion time = (max. # of steps) x (TCLOCK) tmax_conv = (28-1) x (0.4µs) = 102µs.
Average conversion time = 102µs/2 = 51µs
Digital ramp ADC “rounds-up”
A Flash or successive approximation ADC would have output values of =
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44. Example Problems
Why were the digital outputs the same for parts a) and b) of question 1?
Because the difference in the two values of VA was smaller than the resolution of the converter.
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45. Example Problems With 12 bits, percentage resolution is
An ADC has the following characteristics: resolution of 12 bits, full scale error of 0.03%, and full scale input of 5 V. What is the quantization error in volts? What is the total possible error in volts?
With 12 bits, percentage resolution is
(1/(212-1)) x 100% = 0.024%.
Thus, quantization error = 0.024% x 5V = 1.2mV.
Error due to 0.03% inaccuracy is
0.03% x 5V = 1.5mV.
Total Error = 1.2mV + 1.5mV = 2.7mV.
ECE M. A. Jupina, VU, 2014

46. Example Problems
A data acquisition system is being used to digitize an audio signal. The sampling frequency is 20 KHz. Determine the output frequency that will be heard for each of the following input frequencies?
5 KHz < FMAX, 5 KHz
10.1 KHz > FMAX, 9.9 KHz
10.2 KHz > FMAX, 9.8 KHz
15 KHz > FMAX, 5 KHz
19.1 KHz > FMAX, 900 Hz
19.2 KHz > FMAX, 800 Hz
FMAX = FSAMPLING/2 = 20 KHz/2 = 10 KHz
If F > FMAX, then FALIAS = FSAMPLING - FINPUT
ECE M. A. Jupina, VU, 2014

47. Example Problems
The figure below shows the waveform at VAX for a 6-bit successive approximation ADC with a step size of 40 mV during a complete conversion cycle. Examine this waveform and describe what is occurring at times t0 to t5. Then determine the resultant digital output.
ECE M. A. Jupina, VU, 2014

48. Example Problems Full scale input = (26-1) 40mV = 2.52V
t0: Set MSB (bit 5); t1: Set bit 4; clear bit 4; t2: Set bit 3; clear bit 3;
t3: Set bit 2; t4: Set bit 1; clear bit 1; t5: Set LSB;
Digital result = = Thus 1.48 V < VA < 1.52 V
VA – analog input voltage.
37 x 40 mV = 1.48V
38 x 40 mV = 1.52V
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49. ADC0804 Eight-Bit Successive-Approximation ADC with Tri-State Outputs
ADC used in the practicum assignment
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50. ADC0804 Block Diagram See the datasheet for details
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51. ADC0804 Specifications
It has two analog inputs, VIN(+) and VIN(-), to allow differential inputs.
Eight bit resolution at the output. The digital outputs are tri-state buffered for bus interfacing.
VREF/2 pin is for a precision voltage source.
Separate ground connections for digital and analog voltages (for noise considerations).
It has an internal Schmitt Trigger oscillator that can be configured with an external R and C for self-clocking or an external clock can be used. Typical clock frequency is 640 KHz. Higher frequencies possible but error increases.
Typical conversion time is 100 ms or 0.1 ms.
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52. ADC0804 Control Pins INPUTS
Chip Select, , must be LOW for and inputs to have any effect. With HIGH, the digital outputs are in the Hi-Z state and no conversions can take place.
READ, , must be LOW to enable the digital output buffers.
WRITE, , when a LOW pulse is received at this input, a new conversion starts.
OUTPUT
INTERRUPT, , will go HIGH at the start of a conversion and will return LOW to signal the end of a conversion.
ECE M. A. Jupina, VU, 2014

53. sampling rate = conversion rate = fCLK/64.
Self-Clocking the ADC0804
An external clock can be used to establish the timing for the IC or an external resistor and capacitor can be used to set the oscillation frequency of the internal Schmitt Trigger oscillator.
sampling rate = conversion rate = fCLK/64.
ECE M. A. Jupina, VU, 2014

54. An Application of an ADC0804
Example of the ADC0804 interfaced to a microprocessor.
Full handshake between processor and ADC.
Data Request: low-going pulse in Write Signal.
Data Ready: falling edge in INTR Signal.
A conversion starts on the rising edge of WR signal when INTR is HIGH and CS is LOW. EOC occurs when INTR goes low.
The data can be read when CS and RD are LOW.
ECE M. A. Jupina, VU, 2014

55. ADC Circuit in Free Running Mode
LSB
MSB
The A/D converter may be operated in the free running mode by connecting the INTR output to the WR input. Initially, WR will need to be forced LOW to initiate the free running mode, but once started, the response of INTR will cause the triggering of the next conversion cycle. The above timing diagram shows the typical response of the A/D converter in the free running mode. Initially, the ADC is turned off by the WR input at a HIGH. When WR drops to a LOW, the ADC is reset. When WR goes HIGH, the A/D converter starts its conversion of the analog input signal. After 64 clock cycles, the INTR goes LOW for 8 clock cycles, forcing reset (when CS and WR are LOW) and causes the output latches to latch onto the new data. The new output data is the result of the conversion (after 64 clock cycles). Since CS and RD are tied LOW, the INTR is automatically returned to a HIGH, hence starting the next conversion cycle.
NOTE: 72 clock cycles (8 + 64) are actually needed for a complete conversion cycle in the free running mode.
sampling rate = conversion rate = fCLK/72
ECE M. A. Jupina, VU, 2014

56. Appendix: Schmitt-Trigger Inverter
Note the hysteresis symbol on the Schmitt Trigger Inverter
Accepts slow changing signals and produces a signal that transitions quickly.
A Schmitt trigger device will not respond to an input until it exceeds the positive or negative going threshold.
There is a separation between the two threshold levels. This means that the device will “remember” the last threshold exceeded until the input goes to the opposite threshold.
(a) If input transition times are too long, a standard logic device-output might oscillate or change erratically; (b) a logic device with a Schmitt-trigger type of input will produce clean, fast output transitions.
ECE M. A. Jupina, VU, 2014

57. Schmitt-Trigger Inverter Operation
VOH
VOL
VTL
VTH
VOUT
VIN
As VIN increases, VOUT = VOH until VIN > VTH
then VOUT = VOL
When VIN begins to decrease, VOUT = VOL until VIN < VTL
then VOUT = VOH
Hysteresis graph is shown.
ECE M. A. Jupina, VU, 2014

58. Schmitt-Trigger Oscillator
IIN
Manufacturers’ equations are given (assumption is that the input current is not zero).
ECE M. A. Jupina, VU, 2014

59. Analysis of a Schmitt-Trigger Oscillator
VC(t)
VTH
VTL t
VOH
VOUT(t)
VOL TL TH
t = t = 0'
Assume Iin = 0, thus IR(t) = IC(t)
In this analysis we will assume that the input current is zero in order to calculate fosc.
Capacitor Discharging
Capacitor Charging
VC(t)
VC(t)
VOL
VOH
ECE M. A. Jupina, VU, 2014

60. Analysis of a Schmitt-Trigger Oscillator Continued
Capacitor Discharging
Capacitor Charging
Since TH < TL the duty cycle is less than 50%.
ECE M. A. Jupina, VU, 2014

61. Example: Show how to use a 74LS14 Schmitt-trigger inverter to produce an approximate square wave with a frequency of 10 KHz.
Solution:
ECE M. A. Jupina, VU, 2014

62. PSPICE Simulation of a Schmitt-Trigger Oscillator (7414)
TTL 7414 Hex Inverter – unused inputs on the IC are tied to ground to reduce noise in the circuit.
Analog output signal and the voltage signal across the capacitor is shown on the bottom.
Digital output signal representation is shown on the top.
VTH=1.7V and VTL=0.9V.
VOH=3V and VOL=0.1V.
For simulation purposes, the initial condition on the input is set to zero volts (IC=0).
ECE M. A. Jupina, VU, 2014