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9th Workshop on Electronics for LHC Experiments
A CMOS low power, quad channel, 12 bit, 40Ms/s pipelined ADC for applications in particle physics calorimetry Gonçalo Minderico 9th Workshop on Electronics for LHC Experiments
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9th Workshop on Electronics for LHC Experiments
Outline System Introduction ADC Macro Pipeline Architecture Design Details Experimental Results Summary & Planning 9th Workshop on Electronics for LHC Experiments
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9th Workshop on Electronics for LHC Experiments
System Introduction System architecture Mode Bus speed [MW/sec] # buses / Bus width 0 – Quad ADC 80 DDR 2/12 1 – Ecal Direct 40 1/14 2 – Ecal with Hysteresis 3 – Ecal Direct 1/7 4 – Ecal with Hysteresis 5 – Transparent (0-1 ch) 6 – Transparent (2-3 ch) Operating Modes Key factors Low power consumption; high resolution; high speed Input sampling rate 40Ms/s Input signal bandwidth 5MHz Channel selection Radiation tolerant implementation 9th Workshop on Electronics for LHC Experiments
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9th Workshop on Electronics for LHC Experiments
ADC Macro Pipeline Architecture Pipeline Architecture Stage Resolution Tradeoff > Nbit/stage better static linearity more complex blocks Less modularity < Nbit/stage fastest time response worst static linearity simple to implement FE 2b5 : area=0.38mm2; power=9.7mW BE 1b5 : area=0.095mm2; power=1.9mW 9th Workshop on Electronics for LHC Experiments
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Pipeline Architecture
MDAC1b5 a) Gain=2 b) Flash output=2bit c) Flash SH not necessary 9th Workshop on Electronics for LHC Experiments
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9th Workshop on Electronics for LHC Experiments
Design Details 2b5 MDAC opamp schematic 9th Workshop on Electronics for LHC Experiments
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9th Workshop on Electronics for LHC Experiments
Design Details Non-idealities Comparator offset MDAC gain error Thermal noise Gain >4 Comp offset > Vref/8 Gain <4 9th Workshop on Electronics for LHC Experiments
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9th Workshop on Electronics for LHC Experiments
Experimental Results ADC Specs Definition 9th Workshop on Electronics for LHC Experiments
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9th Workshop on Electronics for LHC Experiments
DNL/INL Results Internal references are disabled on following tests VREF layout routing problem limits ADC performance DNL < 0.7LSB INL < 1.5LSB Fs=40Ms/s; Fin=2.5MHz 9th Workshop on Electronics for LHC Experiments
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9th Workshop on Electronics for LHC Experiments
SNR Results Supply 2.5V Fs=40Ms/s SNR [dB] vs Input signal freq [MHz] Fs=40Ms/s Fin=2.5MHz SNR=68dB SNDR=67dB ENOB=10.8bit SNR [dB] vs Input signal ampl [dBFS] 9th Workshop on Electronics for LHC Experiments
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Channel Signal Rejection
Signal coupling between ADC adjacent channels was measured FS 2.5MHz input signal on ADC2 Worst case signal rejection measured on ADC2 –75dBFS 9th Workshop on Electronics for LHC Experiments
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9th Workshop on Electronics for LHC Experiments
Chip Micrograph VCM IBIAS VREF FE STG BE STG CLK DIG CORR DGI DCP Performance Summary 12 bit Quad Pipeline ADC 0.25um CMOS 1P3M 2.5V 40Ms/s Fin=2.5MHz SNR=68dB SNDR=67dB SFDR=70dB DNL/INL< 0.7/ 1.5LSB Area=3.96mm2/2ADC Die size=11.8mm2 DCP area 0.29mm2 (1.18nF) 412mW power 2.5V (4ADCs + VCM & BIAS) 144pin fpBGA Package 150mW power dissipation per channel (gain amplif + dig. log.) 9th Workshop on Electronics for LHC Experiments
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9th Workshop on Electronics for LHC Experiments
Monolithic ADCs Published Papers Fs [Ms/s] Resolution [bit] SNDR [dB] ENOB [bit] Power [mW] EC [pJ] Tech Sharifq M. Jamal ISSCC02 120 10 56.8 9.1 234 3.5 0.35um CMOS Daisuke Miyazaki 30 56 9 16 1 0.3um 2P3M CMOS Suhas Kulhalli 21 12 68 11 35 0.8 0.6um 2P MOS Mikko Waltari 50 13 ND 715 0.35um BICMOS Byung-Moo Min ISSCC03 80 58 9.3 70 1.3 0.18um 2P5M CMOS Sang-Min Yoo 150 54 8.6 123 2 0.18um 1P CMOS Boris Murmann 75 290 1.8 0.35 CMOS Alfio Zanchi 14 71 11.5 900 4.4 BICMOS (SiGe) This Work 2003 40 103 1.25 0.25um 1P3M CMOS 9th Workshop on Electronics for LHC Experiments
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Radiation Tolerant Layout
Layout area overhead due to radiation tolerant structures Cascode NMOS Cascode PMOS Layout area overhead Switches: 23% NMOS cascode compared to CMOS cascode shared drain: 25% Drain region not shared W>14um =>same area W ~ 4um =>3X larger CMOS Switches 9th Workshop on Electronics for LHC Experiments
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9th Workshop on Electronics for LHC Experiments
Summary A competitive ADC macro implementation was shown: Quad 12bit 40Ms/s low power Test chip implemented proving design on spec for external references: 40Ms/s Power consumption of 4 channels is less than 1 channel of previous implementation 9th Workshop on Electronics for LHC Experiments
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9th Workshop on Electronics for LHC Experiments
Status & Planning Prototype submitted for Fab in March 2003 Manufacturing, packaging and system evaluation to end of September 2003 Circuit revision and optimization on going Engineering run submission mid October 2003 5000 production chips for final system assessment expected for early 2004 9th Workshop on Electronics for LHC Experiments
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