Presentation is loading. Please wait.

Presentation is loading. Please wait.

Detectors and read-out DetectorNo. of ch.Read-out method Device candidates CsI(Tl)768Flash ADCCOPPER + 65 MHz FADC FINESSE Active Polarimeter600 x 12 x.

Similar presentations


Presentation on theme: "Detectors and read-out DetectorNo. of ch.Read-out method Device candidates CsI(Tl)768Flash ADCCOPPER + 65 MHz FADC FINESSE Active Polarimeter600 x 12 x."— Presentation transcript:

1 Detectors and read-out DetectorNo. of ch.Read-out method Device candidates CsI(Tl)768Flash ADCCOPPER + 65 MHz FADC FINESSE Active Polarimeter600 x 12 x 2 = 14400 QTC + Pipeline TDC COPPER + QTC + FPGA TDC FINESSE MWPC~200QTC + Pipeline TDC COPPER + QTC + FPGA TDC FINESSE GEM ?QTC + Pipeline TDC COPPER + QTC + FPGA TDC FINESSE Active Target (MPPC?) ~500QTC + Pipeline TDC COPPER + QTC + FPGA TDC FINESSE Counters~120QTC + Pipeline TDC Pipeline HR-TDC COPPER + QTC + FPGA TDC FINESSE COPPER + HR-TDC FINESSE

2 QTC QTC : Charge to time converter –ICRR SK group have developed QTC ASIC since 2004. –Practical version of QTC will develop this year. –Production of QTC will go in 2008. –KEK group is developing ASIC for charge measurements.

3 ICRR SK group ’ s slides (signal processing)

4 ICRR SK group ’ s slides (basic performance of QTC ASIC)

5 ICRR SK group ’ s slides (linearity of QTC)

6 ICRR SK group ’ s slides (time resolution of QTC)

7 ICRR SK group ’ s slides (Read-out board Q-bee)

8 Device Candidates (Pipeline TDC) TDC for Chambers and Counters –FPGA base TDC FINESSE Same hardware with MWPC encoder 1GHz counting / 1nsec resolution –4 different phase 250 MHz clock 32 ch / card Basic components are working. –AMT-FINESSE Timing resolution : 0.78 ns/bit Dynamic range :17 bit 24 ch / card Ready

9 Device Candidates(FADC) FADC for CsI(Tl) charge –65MHz FADC-FINESSE 65 MHz sample, 12bit FADC 8ch / card Differential input self trigger-acceptable

10 Device Candidates (HR-TDC) High resolution TDC for TOF –acam TDC chip, TDC-GP2, TDC-GPX TDC-GP2 : 50ps rms resolution, 1.8msec measurement range –High speed TMC ASIC ~30 psec resolution (aim) R&Ds are progressing in KEK

11 Research schedule 20072008200920102011 QTCDebugging by ICRR person Negotiation with ICRR person Develop modules production HR-TDCEvaluation acam chip and KEK ASIC Develop modules production FADC for CsI(Tl) Read-out test with CsI(Tl)Modify for TREK detectors production FPGA TDC Develop and debugging Modify for TREK detectors production

12

13 KEK-VME System - A Versatile Read-out System - KEK-VME crate VME crate with extended power supply Front-end daughter card 500MHz, 8bit FADC 65MHz, 12bit FADC TMC … Read-Out module KEK-VME G.G/C.G. KEK-VME general I/O (NIM/ECL/LVDS) Read-out part Trigger part (Replace for NIM module)

14 Read-out module (COPPER) COPPER 9U euro card(VME) 4 Front-end A/D card slot Processor PMC slot (on-board PC) Trigger module slot general PMC slot VME-32 interface 1MB x 4 FIFO 32bit 33MHz PCI bus 2 network interface –Processor module –On-board NIC A/D card slot Trigger module Slot (PMC) PMC slot (Processor) PCI (PMC) VME Network Radisys EPC-6315 800 MHz Pentium IIIm Up to 512 MB SDRAM with ECC. 10/100 BaseT Ethernet port On-board Compact Flash socket. 32-bit 33/66 MHz PCI bus interface. Standard Linux working


Download ppt "Detectors and read-out DetectorNo. of ch.Read-out method Device candidates CsI(Tl)768Flash ADCCOPPER + 65 MHz FADC FINESSE Active Polarimeter600 x 12 x."

Similar presentations


Ads by Google