1. 1 Neutron Monitor Workshop 3(B): Next Generation Readout Board Mahidol University January 6, 2010 Paul Evenson University of Delaware Bartol Research Institute

2. 2 Workshop Series Idea Introduce students to technical aspects of neutron monitor operation Rotating workshop series that will repeat every two years at a two per year rate Independent enough so students can join at any point Accommodate wide skill range with an emphasis on “hands on” experience and individual discussion

3. 3 Workshop Series Plan 1.Detector operation A.Detector Physics and Analog Electronics B.Art and Science of Soldering 2.Digital Circuits A.Principles of Digital Logic B.Neutron Monitor Digital Electronics 3.Microcontrollers A.Principles and the Demo Board B.Next Generation Readout Board 4.Real time data acquisition A.Principles of Telemetry and Data Acquisition B.Data Conversion and Manipulation with Visual Basic

4. 4 Plan For Today Lecture with Demonstrations –Questions and answers Describe Design Problem –Questions and answers Individual work on design problem –Only one DEMO908 system here

5. 5 Why Focus on the Readout Board? There are many microcontrollers in the system so focus on one Logical choice might be the Remote –Remote 616 is actually most complex –Connection to physics is closest –David really wants a “700” version New readout board easier to program –More modern microcontroller –Reprogrammable on the board

6. 6 System Overview

7. 7 Remote units continuously –Count neutrons –Collect a sample of pulseheights –Calculate time delays between events Once per second the GPS sends a pulse to the master boards Masters send a “sync” command to the remotes Remotes format data as of the time of the sync and resume taking data Masters request and collect data from the remotes Readout board requests and collects data from the Masters, the Counter Board, and the GPS board Readout board records data locally and also transmits to computer Computer can ask for playback of recorded data

8. 8 Readout Board Schematic: Flash Memory, Two Microcontrollers, and Interfaces

9. 9 Data Flow (Processor) A discovers that a board has data available A captures the data in its RAM A “B64 encodes” data and puts in FIFO1 B retrieves data from FIFO1 B writes data to flash memory B puts data into FIFO2 A sends data from FIFO2 to computer

10. 10 Aside: B64 Encoding Binary data present difficulties in handling and storage Primarily, one cannot have delimiters, because any bit pattern is allowed Chop up three bytes into four groups of six bytes Represent each group by a printing ASCII character Less efficient use of storage but now a whole range of formatting characters and delimiters are possible

11. 11 Why this convoluted scheme? (Processor) A discovers that a board has data available A captures the data in its RAM A “B64 encodes” data and puts in FIFO1 B retrieves data from FIFO1 B writes data to flash memory B puts data into FIFO2 A sends data from FIFO2 to computer

12. 12 Some Answers No solution is perfect Limited resources on each controller Read/Write Memory 2kB –Use external FIFO I/O Ports – one SCI and one SPI –SCI (asynchronous) for computer –SPI (synchronous) for flash memory and for the other boards in the card cage

13. 13 First In First Out (FIFO) Memory The FIFO allows a data source and a data user to operate asynchronously This device stores up to 4096 9-bit “words” with minimal control overhead There is no addressing – the words are read out in the order in which they are put in – “First In – First Out”

14. 14 FIFO Inputs and Outputs Inputs –Data lines D0 … D8 –Write strobe (-W) –Read strobe (-R) –Master Reset (-MR) –Grouping (-RT, -XI) Outputs –Data lines Q0 … Q8 –Empty (-EF) –Half Full (-HF) –Full (-FF)

15. 15 Synchronous Transmission Explicitly clocked data Simple and fast No need for accurate frequency Needs at least two “wires” Shift registers and common clock

16. 16 Asynchronous Transmission Computer COM Ports Use RS 232 Protocol [Known data width, 8bits] with NRZ encoding The stop bit is used to bring [or insure] the signal rests at a logic high following the end of the frame Must have some framing gaps Still need internal patterns for synchronization of character strings For strict ASCII data, and/or are typical Complicated logic to retrieve clock from data

17. 17 SPI Communication During an SPI transmission, data are simultaneously transmitted (shifted out serially) and received (shifted in serially). Serial clock synchronizes shifting and sampling on the two serial data lines. “Slave select” line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate multiple-master bus contention.

18. 18 The SPI is Simple, Really? Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI pin under the control of the serial clock. (See Figure 13-3.) SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. (See 13.13.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. As the byte shifts out on the MOSI pin of the master, anotherr byte shifts in from the slave on the master’s MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the SPTE bit.

19. 19 Readout Board Complication The SPI is almost compatible with our (historical) method of reading the other boards. It is like standard SPI but not quite Our “load” is not implicit in the start of the clock, but is a separate line The clocking phase is wrong This circuit translates the “Processor A” SPI convention to our convention

20. 20 Memory Card Complication SPI signals are completely compatible with the flash card operating as a slave Flash card runs at 3.3 volts so level shifters are needed

21. 21 SCI (Interface to Computer) Receiver and Transmitter are separate devices The receiver is more complicated because it must figure out all of the timing

22. 22 Communication with Computer Because you never know when input will come in you must keep checking Output is simpler

23. 23 Demonstration: Fix Micromonitor “Bug”

24. 24 Design Problem: Is this really the best way to do B64 encoding?