1. Verilog® HDL -Parameters -Strings -System tasks
Sharif University of Technology
Department of Computer Engineering
Verilog® HDL -Parameters -Strings -System tasks
Alireza Ejlali

2. Parameters module testbench; reg aa,bb; wire cc1,cc2;
defparam g1.delay=3;
and_gate g1(aa,bb,cc1);
and_gate g2(aa,bb,cc2);
initial
begin
aa=1'b0; bb=1'b0;
#4 aa=1'b1; bb=1'b0;
#4 aa=1'b1; bb=1'b1;
#4 aa=1'b0; bb=1'b1;
#4 aa=1'b0; bb=1'b0;
end
endmodule
module and_gate(a,b,c);
input a,b;
output c;
reg c;
parameter delay = 2;
or b)
begin
# delay
c=a & b;
end
endmodule

3. String A useful method to show data. 8-bits required per character
Example:
“ab” is equal to ’b _
8-bits required per character
reg [8*18:1] string_value; // Note that this is a vector
initial
string_value = “Hello World!”;
Escaped characters
\n: newline \t: tab
%%: % \\: \
\”: “ \ooo: character number in octal

4. System Task Standard routine operations provided by Verilog
Examples:
Displaying on screen
Monitoring values
Stopping and finishing simulation
All start with $
Example
$display
$monitor
$time

5. $display Displays values of variables, strings, expressions.
Syntax: $display(p1, p2, p3, …, pn);
p1,…, pn can be quoted string, variable, or expression
Adds a new-line after displaying pn by default
Example:
$display(“V = %b”, V);
$display("%m");

6. Format Specification

7. $display Examples
$display(“At time %d virtual address is %h”, $time, virtual_addr);
Output: At time 200 virtual address is 1fe000001c
$display(“Hierarchical name of this module is %m”);
Output: Hierarchical name of this module is top.i1
top: module name
i1: instance name
$display(“A \n multiline string with a %% sign.”);
Output: A multiline string with a % sign.

8. $monitor $monitor: monitors a signal when its value changes.
Syntax: $monitor(p1, p2, p3, …, pn);
p1,…, pn can be quoted string, variable, or signal names
Format specification just as $display
$monitor needs to be invoked only once (unlike $display)
Only one $monitor (the latest one) can be active at any time
$monitoroff to temporarily turn off monitoring
$monitoron to turn monitoring on again

9. $monitor Example initial begin
$monitor($time, “Value of signals clock=%b, reset=%b”, clock, reset);
end
Output: 0 value of signals clock=0, reset=1 5 value of signals clock=1, reset=1 10 value of signals clock=0, reset=0

10. $stop and $finish $stop: stops simulation
Simulation enters interactive mode when reaching a $stop system task
Most useful for debugging
$finish: terminates simulation
Examples:
initial
begin
clock=0;
reset=1;
#100 $stop;
#900 $finish;
end