1. Power Amplifier Design using ADS
Anurag Nigam

2. Outline Agilent Technologies
Various Topics elaborated in this workshop are
Introduction to Power Amplifier
DC Analysis & Load Line
Bias & Stability
Load Pull Concepts
Load Pull in ADS
Matching using Smith Chart
PA Design & Optimization
PA Fine Tuning
Two Tone Response of PA
Design using Modulated Signals as Input
Power Amplifier Layout
Power Amplifier Design using ADS
Agilent Technologies

3. Role of Power Amplifier in Communications
Transmitter
Receiver
Baseband
Driver PA
Mixer
VCO
Antenna
BPF
Basic Transmitter
Figure shows point to point radio sets used by Cab Drivers to communicate with each other through voice. The signal transmitted by Transmitter is picked by Receiver after it has suffered path loss, attenuation by rain, multiple reflections from trees and buildings.
Receiver has a limit to faithfully receive and demodulate weak signals mixed with noise. Signal received by a receiver has to be few decibels stronger than noise. Thus Transmitter has to assure that for maximum distance between transmitter and receiver, transmitted signal is strong enough to reach the receiver with strength few decibels above noise.
As shown in figure1, Power Amplifier is final gain block in Transmitter that has to raise power level of the signal to compensate for path loss, antenna losses, attenuation due to rain & atmospheric particles and multiple reflections from trees and buildings.
Figure 1: Path Loss, Attenuation and Noise Pick up in the link
Power Amplifier Design using ADS
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4. Requirements from a PA Power Amplifier Specifications
Various requirements from a PA, also referred to as specifications, are as follows
Efficiency- It is the ratio of RF Power generated by a PA to DC Power consumed by a PA (Power Added Efficiency). Handheld devices are usually battery operated and most of battery power is consumed by a PA. Hence its efficiency is expected to be high.
Gain- It is the ratio of Power at the output of PA to that at the input of PA (Power Gain). Driver of PA may have a programmable gain that responds to power control loop of radio. Driver usually being a CMOS differential circuit may work at low power levels. Power Amplifier should have sufficient gain to provide output power in right range.
Efficiency
Gain
Linearity
Ruggedness
Quiescent Current
Stability/
Spurs/
Harmonic Distortion
Power Amplifier
Specifications
Figure 2: Key Requirements from a PA (Specifications)
Linearity- Gain of PA Vs Input Power is constant as long as gain device (transistor) receives sufficient DC Power. In case DC Power gets constrained by DC Supply Voltage or Maximum Current device can carry, a further increase in input power does not increase output power. Hence the gain drops. In other words Output Power does not linearly increase with Input Power. Efficiency goes up with increase in output power and does so sharply when DC Power gets constrained. Thus there is a tradeoff between linearity and efficiency.
Importance of Linearity- Signals modulate amplitude as well as phase of RF Carrier. Thus output power swings around average output power with time. When average power is so high that peak output power drives PA in non-linear region the signal cannot be faithfully recovered. Thus PA has to be backed off to lower output power & efficiency.
Power Amplifier Design using ADS
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5. Requirements from a PA Agilent Technologies
Importance of Linearity- Figure 3 (bottom-left) shows Output Power swing with time in response to Input Power swing. If average output power is high enough to cause peak output power in non-linear region (as shown by shaded region in graph) gain is compressed, output phase is enhanced and output power is non-linear with respect to input power. This causes signal integrity issues.
Ruggedness- In case of mobile communications, antenna mismatches cause power to reflect back into Power Amplifier. In case of TDD systems, transmit and receive takes place at same frequency but in different time slots. During switching times, impedance offered to Power Amplifier at its output is not defined. This may cause power to reflect back into the device and damage it.
Ruggedness of device ensures that it will not get damaged with impedance mismatch at all phases.
Stability/Spur/Harmonic Distortion- High gain of devices (transistors) and poor reverse isolation at low frequency may cause amplifier to oscillate. This appears as unwanted tones in the output spectral band of PA. Also in non-linear region of operation of PA, there may be tones at frequencies multiple of fundamental known as Harmonics. All these unwanted tones in the output of PA are referred to as Spurs.
Quiescent Current- Supply current drawn by a PA when no RF input is applied is called Quiescent Current. Low quiescent current is desirable for longer battery time.
PAE (%)
Pout (dBm)
Phase Change
(degrees)
Gain ( dB )
Input Power (dB)
Output Power (dB)
Time
Distorted
Output
Figure 3: (Left) Response of Power Amplifier Vs Input Power showing distortion at high output power
Power Amplifier Design using ADS
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6. Power Amplifier Specifications
Power Amplifier Design Requirements
Peak RF Output Power : Watt
Peak RF Input Power : mWatt
Source & Load Impedance : 50 Ω
Power Added Efficiency : >30 %
Frequency Band : 730 MHz – 790 MHz
Supply Voltage : V
Device : MRF6S010N
Input Return Loss : <-10 dB
Output Return Loss : <-10 dB
Gain : 20 dB
Power Amplifier Design using ADS
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7. DC Analysis Setup Agilent Technologies Important Note
Most of the Power Transistors are unstable on edge of Smith Chart. While doing DC Analysis or DC Measurements DC Supply (AC Ground) should not be directly connected to the device. It is advisable to use Bias De-Coupling. Power Transistors may also be unstable to open, hence a termination to 50 Ω is recommended through a coupling capacitor. Current drawn by the device is more in case it is unstable. Hence take measures to stabilize the device.
Load
Source Stability Circles
Load Stability Circles
Note that both open and short are unstable
Figure 4: Setup for DC Analysis of a device
Power Amplifier Design using ADS
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8. DC Analysis to fix Load Line
Important Note
Power Delivered & Saturation Drain Current decide device load line. This means that smaller device which saturates at low Drain Current has to deliver power with higher voltage swing and hence higher impedance load line. Device stress in such cases is due to voltage swing limited by Drain to Source breakdown.
Figure 5: Load Line for the device, making sure that breakdown voltage is not exceeded
Power Amplifier Design using ADS
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9. Notes on Load Line Agilent Technologies
Figure shows how to determine load line for the device and establish quiescent current. Computed values can be read from figure 5.
From simulation results in figure 5, gate voltage for desired quiescent current can be read.
Targeted Power
Supply Voltage
Maximum drain current without saturation
Peak Output Voltage
Real Load
Vov + Vt
Bias Current
Load Line Equation
Figure 6: Equations to determine load line and quiescent current
Important Note
Note that peak current is too high to allow us use a surface mount inductor for bias circuit at drain unless we wish to use special wire wound inductors. As gate does not draw current we can use inductor for bias de-coupling at gate.
Power Amplifier Design using ADS
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10. Bias Decoupling & its Importance
Bias RF Decoupling is required as DC supply is RF ground. Connecting directly DC Supply to gate and drain of a device is same as shorting device input and output to ground. Device shorted to ground cannot be matched. Figure 7 shows this effect. Figure 8 shows bias RF decoupling.
Load Match
Vdd + _
Vgg
Equivalent AC Circuit
Load Match
Vdd + _
Vgg
RFC
Figure 8: Device Biasing with RF Decoupling
Figure 7: No Bias Decoupling is same as shorting drain and gate to ground
Power Amplifier Design using ADS
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11. Various Forms of Bias Decoupling
RF Short
RF Open
RF Shot
RF Open
Transmission
Line
RF Open
Radial Stub
RF Shot
RF Open
Figure 9: Various circuit topologies for Bias RF Decoupling
Transmission
Line
Power Amplifier Design using ADS
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12. Substrate Selection Agilent Technologies
Most important issues of Power Amplifier Design are – (a) Power Handling Capability & (b) Power Dissipation. The choice of substrate, transmission line dimensions and heat sink design are based on peak CW Power and Efficiency of Power Amplifier.
Figure 10 shows device grounding and heat sinking scenario. Pocket is cut into the laminate and device is directly soldered to the brass metal heat sink. Electrical grounding is provided to the device through brass metal heat sink connected to SMA Connector body.
Laminate has to be selected based on
Pocket in the substrate to ground the device
Brass Metal Heat Sink
Edge Mount SMA Connector
Thermal Dissipation- Temperature rise of the laminate is based on thermal resistance of device package and bond between device package body and heat sink. Coefficient of expansion of laminate has to be matched to metal. Thermal breakdown of the laminate has to be high. Laminate should not soften with heating and should have low thermal resistance.
Figure 10: Device Grounding & Heat Sink Example
Dielectric Constant- For medium frequency applications, high dielectric constant can be chosen to keep distributed passive structures small. Dielectric constant should not vary much with temperature and frequency.
Loss Tangent- To keep dielectric losses small low dielectric loss tangent material should be used.
Manufacturability- Substrate should be easy to cut & electroplate and be mechanically stable.
Power Amplifier Design using ADS
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13. Rogers TMM (Thermoset Microwave Materials)
We will use TMM10l Laminate from Rogers for this project. Some of the key properties of this material are
Substrate Height (15 mil to 125 mil): mil
Dielectric Constant:
Loss Tangent:
Metal Thickness (1/2 to 2 Oz): 1 Oz (1.34 mil)
Peak device drain current is 1.75 A. We will bias the device at A. Usually, upon mismatch device draws 150% of the peak current value. Hence drain current can be as high as 2.62 A. Using Linecalc we design 50 Ohm line as shown in figure11.
CPWG Design
Figure 11: CPWG Design for TMM10l 15 mil high laminate
Power Amplifier Design using ADS
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14. Drain Bias RF Decoupling
Figure 13: S-Parameter response of Bias RF Decoupling Circuit
Figure 12: ADS Setup to simulate Bias RF Decoupling
Use Microstrip Lines to connect various Capacitors and Inductors used in Bias RF Decoupling design. In order to use Microstrip Line models define MSUB. Simulate S-Parameters across the frequency band. Load is 17Ω & decoupling impedance of 65Ω is sufficient.
Power Amplifier Design using ADS
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15. S-Parameter Simulation Setup
Figure 14: S-Parameter Simulation Setup and Small Signal Stability Analysis
Using components from Component Library set up the circuit and simulation as shown in figure14. Resistor is used for bias RF decoupling at gate as MOSFET does not draw any current in gate SMT Coilcraft inductors can safely tolerate 2.5 A of current. By-pass capacitors are usable up to 50 V DC.
Power Amplifier Design using ADS
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16. Small Signal Stability
Absolutely Stable Device
Figure 15: Small Signal S-Parameter Response of unmatched device.
S11 & S22 are input output reflection coefficients in 50Ω system i.e. when termination is the center of smith chart. For device to be stable their magnitudes should be less than 1. Load Stability and Source Stability Circles are contours at a frequency that represent impedances for which load and source reflection coefficients respectively are 1. If center of smith chart is outside these circles and S11&S22 magnitudes are less than 1 then the region outside load and source stability circles is stable. If center of smith chart is enclosed in stability circles and S11&S22 magnitudes are less than 1 then the region inside load and source stability circles is stable.
Power Amplifier Design using ADS
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17. Small Signal Match Agilent Technologies
Figure 16: Small Signal Match & Stability
Low pass input & output match can be designed using 50Ω CPWG Lines and capacitors as shown in the figure. Load & Source Stability Circles demonstrate that matched device is stable from small signal point of view.
Power Amplifier Design using ADS
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18. Small Signal Amplifier
Figure 17: Small signal matched device & small signal stability
Matched device is stable to small signal input both in band and out of band. Both input and output are conjugate matched to 50Ω. We will match the device better for large signal performance using hybrid parameters and load pull.
Power Amplifier Design using ADS
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19. Large Signal Simulation Setup
Ideal Coupler to compute large signal reflection coefficient
Ideal Coupler to compute small signal reflection coefficient
Figure 18: Harmonic Balance setup to simulate across power & across frequency performance of small signal tuned Power Amplifier.
Harmonic Balance simulation setup shown in figure 18 can be used to simulate Gain, Gain Compression, Return Losses and Stability with Large Signal Input.
Power Amplifier Design using ADS
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20. Large Signal Stability & Match
Figure 19: Gain Compression, Input / Output Match & Return Losses across Frequency & Power
Most important information in the figure is variation of input and output match with input power and frequency. Large signal stability factor K>1 shows that across frequency and input power, small signal match PA is stable and meets return loss requirements. Figure also shows 1 dB gain compression point across frequency band.
Power Amplifier Design using ADS
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21. Single Tone HB Simulations
Figure 20: Harmonic Balance Simulation Setup to simulate single tone performance of small signal tuned PA
To understand significance of Large Signal Match we simulate how small signal match affects PA Efficiency and Linearity. Set up the simulation as shown in figure 20 and perform harmonic balance simulations.
Power Amplifier Design using ADS
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22. Single Tone Across Power Performance
Note that roles of load match are
to provide impedance to the device so as to deliver maximum power (i.e. maximum voltage and current swings for the device)
to keep the device voltage and current swings out of phase for low device dissipation.
to transform the voltage and current phases between the device and load such that maximum swing is achieved across the load. Low stored power (electric & magnetic) in load network.
Load Voltage & Current
Voltage & Current for device
Load Voltage & Current
Voltage & Current for device
High device loss
Low device loss
Figure 21: PA Efficiency and 1 dB Compression
Power Amplifier Design using ADS
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23. Ideal Scenario for Efficiency & Output Power
From figure 21 observe that for delivery of power only voltage and current swings in a device are required. It is the role of a load network to transfer efficiently the power to the output i.e. without storing reactive power and dissipating it to ground.
The device may show right voltage and current swings but power delivered to load may be small. This depends on how far voltage & current swings are from an ideal load line (definitely they are not along the load line through which we computed output power)
Notice that device dissipation is dominant factor in Power Added Efficiency. In case voltage and current swings for device were out of phase and with minimum overlap, device dissipation would be lowest. This can be achieved through Harmonic Tune.
Load pull is a brute force technique to search source and load impedances that result in high gain or efficiency or power delivered. Load pull can be performed to determine input / output impedances at fundamental and harmonics.
Most commonly, harmonics are terminated in load pull simulations to short, open or 50Ω. Practically second and third harmonic terminations to complex impedances can result is superior power added efficiency.
We will use load pull to achieve desired output power & PAE. In case we do not achieve power we will re-adjust load line by increasing supply voltage and device quiescent current. Still if we fail to achieve output power we may have to switch to bigger MOSFET device and follow same design flow.
Power Amplifier Design using ADS
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24. Other Views on Stability
We will view stability of unmatched device using few more instruments available in ADS.
Figure 23: Stability Measures for unmatched device
Figure 22: S-Parameter setup to simulate stability across frequency of unmatched device
For absolute stability of device, Stability Factor has to be greater than 1 and Stability measure has to be positive. For absolute stability Mu and MuPrime that measure distance to nearest instability circle from the center of smith chart has to be greater than 1.
Power Amplifier Design using ADS
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25. Load pull Concepts Agilent Technologies
Load pull or source pull is a technique to present impedances to device output or input so as to achieve match for either optimum gain, power delivered, or power added efficiency. Designer may choose to tradeoff between the three. This technique is desirable when designer has very little insight into the device.
Practically load pull can be performed manually using tuners as shown in figure or using automated setups like Maury or Focus,
To generate various impedances a 50Ω line or waveguide with sufficient length can be loaded with a capacitance at any point so as to move away from center of smith chart and remaining length of line moves the impedance around center along constant VSWR circles.
50 Transmission Line
Signal Generator
Spectrum Analyzer
Power Meter
Power
Sensor
Tuner
DUT
Figure 24: Load Pull Concept to generate impedances
Figure 25: Typical Manual Load Pull
Power Amplifier Design using ADS
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26. What makes sense? Agilent Technologies
Load pull data is meaningful if Gain, PAE and Linearity are viewed at constant delivered power rather than for fixed input power. Let us view response of small signal tuned PA across input power to better understand the point.
We wish to deliver output power between 40 and 44 dBm at an efficiency better than 30%. Best achievement can be to deliver output power of 44 dBm with highest efficiency we can at 1 dB compression point. Let us see if we can use load pull to provide a better match to deliver at least 42 dBm (We can change supply voltage and quiescent current)
Figure 26: Across input power performance of small signal tuned device
Power Amplifier Design using ADS
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27. Load pull Setup Agilent Technologies
For load pull to be effective, device has to receive input power. Thus we use device with conjugate matched input. Figure 27 shows load pull setup.
Conjugate Match
Load Tuner
Figure 27: (Right) Circuit setup to perform load pull
Power Amplifier Design using ADS
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28. Performing Load Pull Agilent Technologies
Constant PAE Contours
Constant Pout Contours
Constant Gain Contours
Load pull region
Figure 28: Load pull simulation results
Figure shows that peak gain and output power can be achieved at same impedance. Load match is different from small signal conjugate load match that results in higher gain. Still we are not aware of device compression at this impedance. Maximum PAE is as high as 54.5%. Maximum PAE requires different load matcht. Trade off can be established between maximum output power, maximum gain and maximum efficiency.
Power Amplifier Design using ADS
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29. Output Match Design Agilent Technologies
If output of device and load have lossless plane between them then transistor impedance at the output is conjugate of the load established in load pull. There are two ways to design match i.e. transforming 50Ω to j or transforming j to 50 Ω. We will choose impedance between best PAE match and best Pout Match. We choose 7.8+j13.5.
We will use tuning to design output match
Figure 29: Load Match design using tuning on CPWG Lines and fixed capacitors
Figure 30: (Right) Simulation response of load match
Power Amplifier Design using ADS
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30. Has anything changed yet? PA Optimization!
Using load match achieved through load pull we perform single tone analysis on Power Amplifier. Please note that we have not improved PA performance at all through Load Pull. This proves that Large Signal Match achieved through ADS setup in figure 18 can be as good as the one achieved through Load Pull.
Figure 32: (Below) Optimized PA Performance
1 dB Compression Point
25 Watt Output Power
51.6 % PAE
Figure 31: PA Performance with Load obtained from Load Pull
To achieve higher power we have to either use larger device or increase the supply voltage and quiescent current.
Power Amplifier Design using ADS
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31. PA Fine Tuning using Tuners
Figure 34: Source Match
Figure 35: Load Match
Various line lengths used for matching, supply voltage and quiescent currents can be enabled for tuning to fine tune compression characteristics, output power and efficiency at 1 dB compression point. Finally PA is operated from 26 V with quiescent current of 1.49 A. PA deliver 43.8 dBm output power at PAE of 51.5 %.
Figure 33: (Left) PA Characteristics fine tuned for PAE, Pout and Gain Compression Characteristics
Power Amplifier Design using ADS
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32. Out-band Emission Agilent Technologies
What is the impact of PA non-linearity on large signal input?
Even order mixing causes out-band components displaced away from the fundamental and can easily be filtered using Band-Pass Filter at the output
Odd order mixing causes in-band and adjacent band components- Inter-modulation and in-modulation components. For simplicity let us consider two tones and third order mixing as shown in figure below
-f2
-f1 f1 f2 1 2
+-(2f2-f1)
+-(2f1-f2)
+-(2f2-f2)
+-(2f1-f1)
Figure 36: Cross Modulation (Inter-modulation) and Co-modulation (In-modulation or AM-AM/AM-PM)
Figure 37: Cross Modulation (Inter-modulation)
Figure 38: AM-AM and AM-PM Non-Linearity
Figure 36, 37 and 38 show source of out-band emission and in-band interference using two tone input to PA. In case of modulated signals a multi-tone case is more suitable.
Due to third order mixing, Third Order Inter-modulation and In-modulation products grow with three times the gain to input power compared to fundamental tones.
Power Amplifier Design using ADS
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33. Two Tone Simulations Agilent Technologies
Figure 39: Simulation Setup and Measurement Equations to simulate two tone performance of PA
It is important here to note that device compresses faster to two tone input unless second harmonic at the output is properly terminated. Reflection of second harmonic back into the device results in faster compression of the device. In the load pull we have performed, we terminated all the harmonics properly to achieve good PAE and Power Delivered numbers.
Power Amplifier Design using ADS
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34. Tone Results & Remarks Agilent Technologies
Note that the device is compressing at 41 dBm instead of 44 dBm. PAE for two tone input is 27.7 % instead of 51.5 %.
TOI=55.7 dBm
All the numbers get halved and it is not computation mistake !
Figure 40: PA Performance to Two Tone Input
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35. PA Linearity & Signal Integrity
Q (t)
Modulates Sine Carrier
Modulates Cosine Carrier
Pout (dBm)
Gain (dB)
Phase
Figure 43: Output Constellation
Gain and Phase response of PA is expected to be flat for ideal power amplification. In case this is not so the output is in error.
There is a permissible %Error Vector that is tolerable and yet the symbol is de-modulated correctly. Larger the number of states, larger the bandwidth and lower the supply voltage, lower is the %EVM that is expected.
Junction Temperature variation can cause time dependent phase and gain variations in TDD System.
I and Q phase imbalance can skew the constellation.
Figure 42: Gain/Phase Performance of PA
Figure 41: QAM 16 Modulated Input to a PA
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36. Power Amplifier Response to Modulated Signal
In order to predict linearity of a Power Amplifier, we need to simulate its performance to Modulated Input. We choose QAM 16 modulated signal. QAM 16 Source is setup as shown in the figure. Ptolemy Simulations are performed to view nature of modulated signal that will be fed to PA.
Figure 44: QAM 16 Source & Simulation
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37. Output of QAM 16 Source Agilent Technologies
Figure 45: Ideal and Raised Cosine Filtered (Band Limited) Constellation.
Figure shows QAM 16 signal. I and Q components modulate carrier sine and cosine components which are added to provide output signal. This is done by a QAM Modulator. Carrier input to QAM modulator is 760 MHz pure tone with desired power level. Bit rate of the signal is 1 MHz and symbol rate is half of that.
Power Amplifier Design using ADS
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38. Output Spectrum of QAM 16 Source
Design component of QAM 16 source with various input parameters.
Figure 46: Output Spectrum of QAM 16 Source
Figure 47: QAM 16 Source
Power Amplifier Design using ADS
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39. Circuit & Ptolemy (DSP) Co-simulation
Simulation Methodology
Create a sub-circuit component for Power Amplifier with design variables namely stop time, step time and frequency
Add Circuit Envelope Controller to the PA Component Circuit
Set the Circuit Envelope Controller to Fast Cosim ( Automatic Verification Modeling or AVM Mode). This will enhance simulation speed.
Set the DSP Simulation by placing QAM Source Component, Power Amplifier Component, EnvOutShort Component at output of PA, Spectrum Analyzers at input and output of PA, attenuator to compensate for PA Gain, QAM demodulator with proper sensitivity ( Vout / Vin ) and TkConstellation Component.
Set Discrete Flow Controller for DSP Simulations
Simulation Details
QAM Source provides input to PA with proper power level
Spectrum Analyzer plots signal spectrum at input of PA
Envelope Selector (EnvOutShort) is placed at the output of PA to interface Analog Circuit to Digital Circuit
Spectrum Analyzer plots signal spectrum at output of Envelope Selector
Output of Envelope Selector is attenuated by same value as gain of PA using a Matched Attenuator
Output of Attenuator is demodulated by QAM Demodulator
TkConstellation Sink plots output constellation
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40. Co-simulation Setup Agilent Technologies
Power Amplifier
Figure 48: Ptolemy Cosim Schematic
Power Amplifier Design using ADS
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41. Power Amplifier Component
Figure 49: Power Amplifier Component for Ptolemy Simulation
Figure shows Analog Circuit for Cosim. Envelope controller is set as shown in the figure. Set the design parameters like Tstop, Tstep and fo.
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42. Fast Cosim Mode Agilent Technologies Figure 51: AVM Mode Settings
Figure 50: Enabling Fast Cosim in Envelope Controller
Enable fast cosim mode in Envelope Controller. Select display variables ABM_Mode, ABM_MaxPower, ABM_AmpPts, ABM_ReUseData. Set the variables as shown in figure 51.
Figure 52: Setting Fast Cosim Properties and Display
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43. QAM Constellation Agilent Technologies
Figure 53: QAM Constellation at input and output of PA operating at peak input power of 23.7 dBm delivering 40.9 dBm of power
Figure shows QAM constellation at output of PA obtained after demodulation. Filter delays have to be adjusted to get proper sampling.
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44. Spectral Analysis Agilent Technologies
Figure 54 and 55 show uncompressed and compressed PA. Note that PA is only 0.3 dB compressed yet we have ACPR of -34 dBc. Major contribution is from AM to PM conversion as PA is expanding. This ACPR may be acceptable depending on system implementation. PA delivers 15 Watt i.e dBm as shown in figure 55.
Figure 54: Uncompressed PA
Figure 55: Compressed PA
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45. Demodulated Constellation at PA Output
Pout = dBm (67 mWatt)
Pout = 41.7 dBm (15 Watt)
Figure 56: Uncompressed PA
Figure 57: Compressed PA
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46. EVM Measurement Setup Agilent Technologies
Figure 58: Co-simulation Setup to simulate EVM & ACPR Across Power
Figure 58 shows simulation setup to simulate % EVM across input power. Spectrum Analyzer is used at the output to measure ACPR. EVM_WithRef measures % EVM.
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47. % EVM & ACPR Results across Power
Figure 59: %EVM and ACPR across input power
Spectrum is plotted for the output power indicated by marker “EVMPercent”. Listed below the figures are %EVM, ACPR, Output Power in dBm (Watt) corresponding to the marker.
Power Amplifier Design using ADS
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48. SMA to CPWG Transition Agilent Technologies
Figure 60: SMA to CPWG Transition & EM Simulation
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49. PA Layout Agilent Technologies Figure 61: PA Layout & 3D Preview
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50. Future Scope Agilent Technologies
EM Simulation of entire layout can be performed followed by EM-Circuit Co-simulation
Load pull can be performed to plot constant ACPR and % EVM Contours
PA can be optimized for linearity
Balanced PA can be designed to scale up the power
Class E and F topologies can be investigated for further improvement in efficiency. Linearity can be achieved by backing off in power level.
If you wish to explore further kindly contact :
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