1. Multiplexers (Data Selectors)
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DIGITAL LOGIC DESIGN
Lecture #12: Multiplexers, Exclusive OR Gates, and Parity Circuits
Multiplexers (Data Selectors)
A multiplexer (MUX for short) is a digital switch:
it passes (connects) one of its data inputs to the output
the data input selected is a function of a set of control inputs called selection inputs S
OUT 1
D0 D1 S D1 D0
OUT 1 D0
data inputs
2-to-1 MUX
OUT D1
Two alternative forms for a 2:1 MUX truth table S
control input
OUT = S·D0 + S·D1
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2. Multiplexers Do Selecting
Selecting of data or information is a critical function in digital systems and computers
Circuits that perform selecting have:
A set of n information inputs Di from which the selection is made
A set of k control (select) lines for making the selection
– A single output
D0 D1 D2 D3 1 2 3 .
n–1 k
n ≤ 2k inputs
OUT
Dn–1
k select lines
Sk–1 … S1 S0
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Multiplexer Analogy
D0 D1 D2 D3 1 2 3
Out
1 0
S S0
(Source: F. Vahid, “Digital Design”, J. Wiley, 2007)
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3. Example Uses of Multiplexers
In computers to select among signals
To implement command:
if A=0 then Z=X·Y else Z=XY
X Y Z 1 A
Trip controller in a car to display mileage, time, speed, etc.
clock
4-to-1 MUX
Display
odometer 1 2
speed
mileage S1 S0
Push button
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Multiplexer Structure
Switch circuit equivalent
Multiplexer is unidirectional
multiplexer
1D0
1D1 1Y
1Dn–1
2D0
2D1 2Y
2Dn–1
enable EN s
select SEL
bD0 bD1
b b
D0 D1 bY b
n data sources Y
data output
bDn–1 b
Dn–1
SEL EN
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4. Example: 4-to-1-line Multiplexer
Expression for OUT:
OUT = S1·S0·D0 + S1·S0·D1 + S1·S0·D2 + S1·S0·D3
M0 M1
2k –1
or: OUT = ∑ Mj·Dj
j = 0
M2 M3
S1 S0
OUT D0 1 D1 D2 D3
Circuit implementation: Sum-of-Products
4 AND gates (4 product terms)
2-to-4 line decoder (to generate the minterms)
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Example: 4-to-1-line Multiplexer
2-to-22-line decoder
22 × 2 AND-OR
D0 D1 D2 D3 M0
Decoder S0 M1 M2
OUT S1 M3
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5. General Multiplexer Equation
A general logic equation for a multiplexer
output:
n1
iY  EN  M j iDj
j0
Logical sum of product terms
Variable iY is a particular output bit (1 ≤ i ≤ b)
Mj is a minterm j of the s select inputs
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Gate Level Implementation of MUXs
positive logic:
negative logic: D1
D1 S D0
■ 2:1 MUX
S D0
OUT
OUT
D0 D1 D2
D0 D1
D2 D3
OUT
OUT D3
4:1 MUX S1 S0 S1 S0
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6. Multiplexer Standard Packaging
IC has limited number of pins (16) n·b + b + s ≤ 16 – 2 in out SEL EN
(n+1)·b + log2 n ≤ 13
n data inputs b bits per input s select inputs
b n s 1 8 3
(12)
8 input 1 bit
74x151 2 4
dual 4 input 2 bit
74x153
(13)
quad 2 input 4 bit
74x157
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Truth table of 74x151
Truth table for 74x input, 1-bit multiplexer
Only “control” inputs are listed under “Inputs”
Outputs specified as 0” or “1”, or a simple logic function of “data” inputs (e.g., D0 or D0)
Inputs
Outputs
EN_L S2 S1 S0 Y
Y_L 1 x D0
D0 D1
D1 D2
D2 D3
D3 D4
D4 D5
D5 D6
D6 D7
D7
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7. 8-input 1-bit Multiplexer
logic diagram and
logic symbol
EN_L
(7)
S0 S1 S2
S0 S1 S2 D0
(4)
D1 (3) D2
(2) D3
(1)
(5) Y
Y_L
(15)
(6) D4
74x151 D5
(14) EN 5 S0 10 S1 9 S2 4 3 D0 Y D1 2 D2 1 D3 15 D4 14 D5 13 D6 12 D7 7 11 D6
(13) D7
(12) 6 S0
(11) S1
(10) S2
(9)
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74x157
2-input 4-bit Multiplexer
 74x157
selects between two 4-bit inputs
74x157 15 1
EN S
1D0
1D1 1Y
2D0
2D1 2Y
3D0
3D1 3Y
4D0
4D1 4Y 4 2 3 7 5 6 9 11 10 12 14 13
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8. 2-input 4-bit Multiplexer
truth table:
Inputs
Outputs
EN_L S 1Y 2Y 3Y 4Y 1 x
74x157
1D0
2D0
3D0
4D0 15
1D1
2D1
3D1
4D1
EN S
1D0
1D1 1Y
2D0
2D1 2Y
3D0
3D1 3Y
4D0
4D1 4Y 4 2 3 7 5 6 9 11 10 12 14 13
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Cascading/Expanding Multiplexers
Large multiplexers can be made by cascading smaller ones
D0 D1 D2 D3
8:1
mux
alternative implementation
4:1
mux
D0 D1
2:1
mux
8:1
mux
2:1
mux
OUT
D4 D5 D6 D7
D2 D3
2:1
mux
4:1
mux
mux
OUT
D4 D5
S1 S0 S2
D6 D7
Control signals S1 and S0 simultaneously choose one of D0, D1, D2, D3 and one of D4, D5, D6, D7
Control signal S2 chooses which of the upper or lower mux's output to gate to OUT S0
S2 S1
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9. Cascading/Expan ding Multiplexers
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Combining four 74x151s to make a 32-to-1 multiplexer
74x138 3-to-8 decoder used as 2-to-4 decoder for two high-order bits to enable one of 74x151s
Multiplexers as General-purpose Logic
A 2n:1 multiplexer can implement any function of n
variables
with the variables used as control inputs and
the data inputs tied to 0 or 1 1 1 2 3
4 8:1 MUX 5 6 7
S2 S1 S0 F
Example:
F(A,B,C) = M0 + M2 + M6 + M7
= A'·B'·C' + A'·B·C' + A·B·C' + A·B·C
A B C
= A'·B'·C'·(1) + A'·B'·C·(0) + A'·B·C'·(1) + A'·B·C·(0) + A·B'·C'·(0) + A·B'·C·(0) + A·B·C'·(1) + A·B·C·(1)
OUT = A'·B'·C'·I0 + A'·B'·C·I1 + A'·B·C'·I2 + A'·B·C·I3 +
A·B'·C'·I4 + A·B'·C·I5 + A·B·C'·I6 + A·B·C·I7
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10. Multiplexers as Function Generators
Multiplexers as General-purpose Logic
Generalization:
data inputs can also be tied to variables not just 0’s an 1’s
I0 I1 …
In–1 In F
four possible configurations of truth table rows can be expressed as a function of In
n–1 mux control variables . .
single mux data variable
0 In In 1
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Multiplexers as Function Generators
We can generate the four possible Z values (0, 1, Z, Z) and realize the function with half the values
Realizing F = ∑X,Y,Z (0,3,5,6) with a 4-input multiplexer:
I0 I1 …
In–1 In
74x153
Y X
(14)
A B 1G
1C0
(2)
Row X Y Z
F 1 1 2 3 4 5 6 7
74x04
(1) Z
(1)
(2)
(6) Z U1
(5)
1C1
1C2
1C3 2G
2C0
2C1
2C2
2C3 1Y
(7)
(4) F
(3) Z
(15)
(10) Z
(11)
(12)
(13) 2Y
(9)
unused Z U2
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11. Demultiplexers 4-variable Function using 8-input Multiplexer Realizing
F = ∑N0,N1,N2,N3 (1,2,3,5,7,11,13)
with an 8-input multiplexer:
Row N N N N0 F
+5V
74x151 N0 R
(7) EN 1 N1
(11)
A B C D0 D1 D2 D3
(10) 4 1
0 N2 (9) 5
(4) N0
N3 N0 6 7 1
Y Y
(5)
(6) F N0
(3)
(2)
(1)
(15) D4 N0
(14) D5
(13) D6 12 1 13 14 15 N0
(12) D7 U1
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Demultiplexers
Route a single input to one of many outputs, as a function of a set of control inputs
y0 y1 y2 y3 y4 y5 y6 y7
1:8
demux x 3
s[2:0]
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12. Demultiplexer Analogy
Demultiplexers
Demultiplexer function is just the inverse of multiplexer’s
A binary decoder with enable input can be used as a demultiplexer
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Demultiplexer Analogy
A MUX driving a bus and a demultiplexer receiving the bus
multiplexer demultiplexer
SRCA SRCB SRCC
DSTA DSTB DSTC
BUS
SRCZ
DSTZ
SRC SEL
DEST SEL
SRCA SRCB SRCC
DSTA DSTB DSTC
BUS
MUX
DMUX
SRCZ
DSTZ
SRC SEL
DEST SEL
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13. Exclusive-OR Gates Exclusive-OR Gates
Exclusive-OR (XOR) gate is a 2-input gate whose output is “1” if exactly one of its input is “1”
– or: XOR gate produces a “1” output if its inputs are
different
Exclusive-NOR (XNOR) or Equivalence just opposite—produces output “1” if its inputs are the same X
XOR:
XNOR:
XY
X  Y = X·Y + X·Y (X  Y) = X·Y + X·Y Y
X Y
(XY)
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Exclusive-OR Gates
Truth table and gate-level implementation
AND-OR implementation: X
F = X  Y X Y
X  Y (XOR)
(X  Y)
(XNOR) 1
three-level NAND implementation:
F = X  Y Y
(X·Y) · (X+Y) = (X+Y) · (X+Y) = X·Y + Y·X
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14. XOR versus XNOR Equivalent Symbols for XOR/XNOR
(XY) = (X·Y + X·Y) = (X + Y) · (X + Y)
= X·X + X·Y + X·Y + Y·Y
= X·Y + X·Y
X  X out  out … the circuit XOR = XOR
(X·Y + X·Y) = X·Y + X·Y
X  X out  out … the circuit XNOR = XNOR
X·Y + X·Y
X  1 = X·0 + X·1 = X
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Equivalent Symbols for XOR/XNOR
XOR gates
XNOR gates
Simple rule:
– Any two signals (inputs or output) of an XOR or XNOR gate may be complemented w/o changing the resulting logic function
X  0 = X X  1 = X
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15. Cascading XOR gates Cascading XOR gates Daisy-chain connection
I1 I2
Sum modulo 2
Parity computation
I3 I4
ODD IN
Balanced tree structure
N–1
I1 I2
log2(N)
I3 I4
ODD
IN–1 IN
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Cascading XOR gates
The tree structure is faster than daisy-chain connection because the gates depth of its treelike structure is log2(N), which is much less than N–1 for a daisy-chain structure
Both are called odd-parity circuits because its output is “1” if an odd number of inputs are “1”
Used to generate and check parity bits in computer systems
Detects any single-bit error
Even-parity circuit has odd-parity circuit’s output inverted—its output is “1” if an even number of its inputs are “1”
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16. Example Parity Computation
F = I1  I2  I3 F = 1 ODD number of “1” in the input I1 I2 I3 F 1
(8) I1 I2
(10)
(9) F I3
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