1. Developments in Electronics for the Upgrade
Pablo Moreno
IFIC-UV
09 December
2011

2. Activities with the GBT protocol in Xilinx
Migration of the GBT code to Xilinx Virtex 6 completed
Code adapted for the instantiation of V6 QUADs instead of V5 DUAL Tiles (VHDL primitives of groups of transceivers sharing common resources)
Studies for 4, 8, 12, 16 and 20 links.
Better results than V5, but still lot of logic and RAM are used

3. Activities with the GBT protocol in Xilinx

4. Activities with the GBT protocol in Xilinx
Started evaluataing Virtex 6 specific parts regarding to resources and price
Virtex 7 is coming, but still Virtex 6 is quite expensive (2000$-7000$)
Spartan 6 has not enough transceivers/logic/memory
Also checking for Kintex 7 (between Virtex 6 and Spartan 6 in resources and price)
Studies about GBT instantiation on these models coming soon