1. Completing the VFTLP Standard Practice
Presented to WG 5.5
9/14/07
Additional Specifications for VFTLP SP
Barth Electronics Inc.

2. TLP was developed primarily as an ESD design tool for HBM and MM protection circuits.
VFTLP was created simply by shortening the TLP pulse in an attempt to analyze CDM protection circuits
Present recommendations in our VFTLP Standard Practice only provide specs on the I-V characteristics of CDM circuits

3. The measurement window location is easy when the waveform is smooth

4. Where does the Measurement Window belong when the voltage or current changes during the test pulse?

5. Unlike HBM, where energy dissipation in silicon in the parameter of primary importance, 75% of CDM failures are gate oxide related
Gate oxides fail from excess voltage
Therefore in CDM, the amount of voltage which bypasses the voltage clamp now becomes the important parameter

6. Waveform Specs are as important an the I-V plot for VFTLP
CDM events and testing occur in Sub-nanosecond times
No one current or voltage is sufficient for CDM design
The time domain response of CDM protection provides a new insight for design
Time domain data doubles the value of VFTLP
Ignoring time domain response parameters ignores half the available data

7. Direct analysis of time domain silicon turn-on characteristics provides information on circuit operation inside the package.
Quantatative measurement of silicon turn-on characteristics is now available
Using very fast time domain measurements, designers can now analyze total circuit operation in sub-nanosecond times

8. Our present VFTLP Standard Practice does not specifically identify voltage or current waveforms as important parameters in CDM analysis.

9. Because VFTLP can make “Very Fast” measurements of CDM protection circuits, our VFTLP Standard Practice can be expanded to use “Very Fast” voltage and current measurements at the DUT.

10. Doubling the value of VFTLP
If Gate Oxides are 75% of Failures:
Then voltage threats are 3 times as important as thermal failures in silicon or metals
For the sake of argument let us limit GOX voltage threat waveforms to twice the value
of I-V data
Sub-nanosecond time domain data provides new insight into GOX voltage threats
Quantatative data on silicon response to very fast threats has not been available
CDM design needs all the help it can get.

11. 75% of CDM Failures occur in Gate Oxides
GOX over-voltage has been approximated with TDDB waveforms
Long term voltages for microseconds or months doesn’t fit the CDM sub-nanosecond threat
CDM treat is not a rectangular pulse
Real GOX threats are not rectangular

12. Typical Voltage Waveforms on Silicon

13. Analysis of the circuit inside the package is available with VFTLP
Breaking the package into its component parts allows each to be analyzed in sub-nanosecond time
Silicon voltage clamp circuits can be measured with VFTLP
Package inductance and capacitance can be measured with VFTLP

14. Adding current, and especially voltage waveforms to VFTLP testing can greatly increase the value of this test.
The CDM event in over in 1 to 2 ns
Semiconductor turn-on is delayed
Voltage overshoot occurs early in the pulse
High Speed time domain analysis of the silicon voltage clamp, along with the package, improves CDM information available from VFTLP

15. Complete VFTLP Specifications
Voltage and current waveforms Require:
Test pulse risetime
Test pulse characteristics
Sensor response specifications
Test pulse delivery at the wafer (and return for TDR)
Adding these to the Standard Practice will provide value to users in CDM design

16. Therefore, information on “Very Fast” time domain measurements should be included in this Standard Practice THE END