80386DX-Basic Programming Model and Applications Instruction Set

80386DX-Basic Programming Model and Applications Instruction Set
Presented by Mr. D P Gaikwad Head, Computer Engineering Department All India Shri Shivaji Memorial Society’s College of Engineering Faculty Development Programme, SPP University, Pune

Course Objectives and Outcomes
To learn the architecture and programmer‘s model of advanced processor. To understand the system level features and processes of advanced processor . To acquaint the learner with application instruction set and logic to build assembly language programs. To understand debugging and testing techniques confined to DX. Course Outcomes: On completion of the course, student will be able to– Apply the assembly language programming to develop small real life embedded application. Understand the architecture of the advanced processor thoroughly to use the resources for programming . Understand the higher processor architectures descended from architecture . Faculty Development Programme, SPP University, Pune

Family tree of 80386 Chip Introduction Data bus Address Bus Memory
4004 1971 4 8 256 Byte 8008 1972 8080 1974 16 64 KB 8086/88 1978 16/8 20 1M 80186/188 1982 80286 1983 24 16M:Clock speed is high 80386 DX(1986:not compatibility) SX(1988: mostly used, Not Co-Processor) DX: pin SX: pin 32 DX:4G (275,000 transistor) SX:16MB 80486 Memory Size: 4G +16K cache Faculty Development Programme, SPP University, Pune

Faculty Development Programme, SPP University, Pune
80286 vs vs 80486 It has like microprocessor and like numeric coprocessor Faculty Development Programme, SPP University, Pune

Difference between 80386 SX/DX
Both have the same internal architecture. Lower cost package and the ease of interfacing to 8-bit and 16-bit memory and peripherals make , SX suitable for use in low cost systems. Faculty Development Programme, SPP University, Pune

Difference between 80386 SX/DX
• Faculty Development Programme, SPP University, Pune

Introduction to 80386 The is an advanced 32-bit microprocessor optimized for multitasking operating systems and designed for applications needing very high performance. The 32-bit registers and data paths support 32-bit addresses and data types. The processor can address up to 4 gigabytes of physical memory and 64 terabytes (246 bytes) of virtual memory. The on-chip memory management facilities include address translation registers, advanced multitasking hardware, a protection mechanism, and paged virtual memory. Special debugging registers provide data and code breakpoints even in ROM-based software. Faculty Development Programme, SPP University, Pune

Features of 80386 The has three processing modes: 1. Protected Mode: Protected mode is the natural 32-bit environment of the processor. In this mode all instructions and features are available. 2. Real-Address Mode. Real-address mode is the mode of the processor immediate after RESET. In real mode the appears to programmers as a fast 8086 with some new instructions. Most applications of the will use real mode. 3. Virtual 8086 Mode: Virtual 8086 mode is a dynamic mode which can switch repeatedly and rapidly between V86 mode and protected mode. The CPU enters V86 mode from protected then leaves V86 mode and enters protected. Faculty Development Programme, SPP University, Pune

Internal Architecture
Faculty Development Programme, SPP University, Pune

Architecture of 80386 The Internal Architecture of is divided into 3 sections: i) Central processing unit (CPU) Execution unit (EU) and Instruction unit (IU) ii) Memory management unit (MMU) Segmentation unit Paging unit. iii) Bus interface unit( BIU) Faculty Development Programme, SPP University, Pune

MEMORY ORGANIZATION AND SEGMENTATION
The physical memory of an system is organized as a sequence of 8-bit bytes. Each byte is assigned a unique address that ranges from 0 to a maximum of 2^32 – 1 (4 Gigabytes). The model of memory organization determined by systems-software designers. Two model of memory 1. Flat model: single array of up to 4 GB. A pointer into this flat address space is a 32-bit ordinal number that may range from 0 to 2^32 -1. Faculty Development Programme, SPP University, Pune

Segmented model: collection of up to 16,383 linear address spaces. Viewed by an applications program (called the logical address space) The processor maps the 64 terabyte logical address space onto the physical address space (4 GB) by the address translation mechanisms. Each of these linear subspaces is called a segment. A segment is a unit of contiguous address space Segment sizes may range from 1 byte up to a maximum of 2^32 bytes (4 gigabytes). Faculty Development Programme, SPP University, Pune

A complete pointer in this address space consists of two parts. l. A segment selector, which is a 16-bit field that identifies a segment. 2. An offset, which is a 32-bit ordinal that addresses to the byte level within a segment. Faculty Development Programme, SPP University, Pune

Execution unit :DATA TYPES
Fundamental data types: Faculty Development Programme, SPP University, Pune

. Faculty Development Programme, SPP University, Pune

Graphically summarizes the data types supported by the 80386.

Registers The has eight 32-bit general purpose registers which may be used as either 8 bit, 16 bit or 32 bit registers. •A 32-bit register known as an extended register, is represented by the register name with prefix E. •Example : A 32 bit register corresponding to AX is EAX •So the general purpose registers of 386 are EAX, EBX, ECX, EDX, EBP, ESP, ESI and EDI Faculty Development Programme, SPP University, Pune

Registers BP, SP, SI, DI represents the lower 16 bit of their 32 bit counterparts, and can be used as independent 16 bit registers. The 16 bit flag register is available along with 32 bit counterpart EFLAGS. •The 16 bit flag register is available along with 32 bit counterpart EFLAGS. Faculty Development Programme, SPP University, Pune

Flag Register The Flag register of is a 32 bit register. Out of the 32 bits, Intel has reserved bits D18 to D31, D5 and D3 and set to 0 While DF is always set at 1. Two extra new flags are added to the flag to derive the flag register of They are VM and RF flags. Faculty Development Programme, SPP University, Pune

Flag Register Faculty Development Programme, SPP University, Pune

VM Bit - Virtual Mode Flag
If this flag is set to VM=1, the enters the virtual 8086 mode within the protection mode. When VM bit is 0, 386 operates in protected mode This is to be set only when the is in protected mode. This bit can be set using IRET instruction or any task switch operation only in the protected mode. Faculty Development Programme, SPP University, Pune

RF-Bit Resume Flag If RF=1, 386 ignores debug faults and does not take another exception so that an instruction can be restarted after a normal debug exception. If RF=0, 386 takes another debug exception to service debug faults This flag is used with the debug register breakpoints. It is checked at the starting of every instruction cycle and if it is set=1, any debug fault is ignored during the instruction cycle. The RF is automatically reset after successful execution of every instruction, except for IRET and POPF instructions Faculty Development Programme, SPP University, Pune

RF- Resume Flag... Also, it is not automatically cleared after the successful execution of JMP, CALL and INT instruction causing a task switch. These instruction are used to set the RF to the value specified by the memory data available at the stack. Faculty Development Programme, SPP University, Pune

STATUS AND INSTRUCTION REGISTERS
Six segments of memory may be immediately accessible to an executing program. The segment registers CS, DS, SS, ES, FS, and GS are used to identify these six current segments. Each of these registers specifies a particular kind of segment, as characterized by the associated mnemonics ("code," "data," or "stack"). Faculty Development Programme, SPP University, Pune

CS Register CS: The segment containing the currently executing sequence of instructions is known as the current code segment. The fetches all instructions from this code segment, using as an offset the contents of the instruction pointer. Faculty Development Programme, SPP University, Pune

SS and ES ,DS,FS,GS Register
SS: Subroutine calls, parameters, and procedure activation records usually require to allocate memory as a stack. All stack operations use the SS register to locate the stack. Data Registers: The DS, ES, FS, and GS registers allow the specification of four data segments. Access different types of data structures; Types of data structures: Current module, Exported data, Dynamically created data structure and data Shared with another task. Faculty Development Programme, SPP University, Pune

Hidden Registers/ Program invisible registers/ Special Registers

Control Registers The has four 32 bit control registers CR0, CR1, CR2 and CR3 to hold global machine status. CR1 is not used in 386 and reserved for future use. Load and store instructions are available to access these registers. Faculty Development Programme, SPP University, Pune

386 control registers 31 Faculty Development Programme, SPP University, Pune

System Address Registers
The 386 supports 4 types of descriptor table: Global descriptor table (GDT), Local descriptor table (LDT), Interrupt descriptor table (IDT) Task state segment descriptor (TSS). Four special registers are defined to hold the base address of these tables Global descriptor table Register (GDTR) Local descriptor table Register (LDTR) Interrupt descriptor table Register (IDTR) Task state segment descriptor Register (TR). Faculty Development Programme, SPP University, Pune

Debug Registers Intel has provide a set of 8 debug registers for hardware debugging. DR4 and DR5 are Intel reserved. The initial four registers DR0 to DR3 store four program controllable breakpoint addresses, DR6 and DR7 respectively hold breakpoint status and breakpoint control information. Faculty Development Programme, SPP University, Pune

Debug Registers DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 RESERVED Linear breakpoint address 0 Linear breakpoint address 1 Linear breakpoint address 2 Linear breakpoint address 3 breakpoint status breakpoint control info Faculty Development Programme, SPP University, Pune 31

Test Registers Two test register are provided by for page caching namely test control and test status register. Faculty Development Programme, SPP University, Pune

INSTRUCTION FORMAT The information encoded in an instruction includes a specification of ; Operation to be performed (Opcode). Type of the operands to be manipulated, Location of these operands. Opcode Source(M/ Reg) Destination(M/ Reg) Faculty Development Programme, SPP University, Pune

INSTRUCTION FORMAT Two-operand instructions of the permit operations of the following kinds: • Register-to-register • Register-to-memory • Memory-to-register • Immediate-to-register • Immediate-to-memory Certain string instructions and stack manipulation instructions transfer data from memory to memory. Push and pop stack operations allow transfer between memory operands and the memory-based stack. Faculty Development Programme, SPP University, Pune

Memory Management Faculty Development Programme, SPP University, Pune

Memory Management The transforms logical addresses (i.e., addresses as viewed by programmers) into physical address (i.e., actual addresses in physical memory) in two steps Segment translation: logical address (consisting of a segment selector and segment offset) are converted to a linear address. Page translation: linear address is converted to a physical address and step is optional. Faculty Development Programme, SPP University, Pune

80386 addressing mechanism Faculty Development Programme, SPP University, Pune

SEGMENT TRANSLATION Figure shows in more detail how the processor converts a logical address into a linear address. Faculty Development Programme, SPP University, Pune

SEGMENT TRANSLATION To perform segmentation translation, the processor uses the following data structures: • Descriptors • Descriptor tables • Selectors • Segment Registers Faculty Development Programme, SPP University, Pune

Descriptors The segment descriptor provides the processor with the data it needs to map a logical address into a linear address. Descriptors are created by compilers, linkers, loaders, or the operating system, not by applications programmers. Faculty Development Programme, SPP University, Pune

Two general descriptor formats

Descriptor bits BASE: Defines the location of the segment within the 4 gigabyte linear address space. LIMIT: Defines the size of the segment. The processor interprets the limit field in one of two ways, depending on the setting of the granularity bit: 1. In units of one byte, to define a limit of up to 1 megabyte. 2. In units of 4 Kilobytes, to define a limit of up to 4 gigabytes. Faculty Development Programme, SPP University, Pune

Descriptor bits Granularity bit: G=0, the limit is interpreted in units of 1 byte. when set=1, the limit is interpreted in units of 4 Kilobytes. TYPE: Distinguishes between various kinds of descriptors. DPL (Descriptor Privilege Level): Used by the protection mechanism . Faculty Development Programme, SPP University, Pune

Descriptor bits Segment-Present bit: If set=0 the descriptor is not valid for use in address transformation. And the processor will signal an exception when a selector for the descriptor is loaded into a segment register. Accessed bit: Set=1, when the segment is accessed; i.e., a selector for the descriptor is loaded into a segment register. Faculty Development Programme, SPP University, Pune

Descriptor Tables Segment descriptors are stored in either of two kinds of descriptor table: • The global descriptor table (GDT) • A local descriptor table (LDT) A descriptor table is simply a memory array of 8-byte entries that contain descriptors. Descriptor table is variable in length and may contain up to 8192 descriptors. Faculty Development Programme, SPP University, Pune

Descriptor Tables Faculty Development Programme, SPP University, Pune

Descriptor Tables The processor locates the GDT and the current LDT in memory by means of the GDTR and LDTR registers. These registers store the base addresses of the tables in the linear address space and store the segment limits. The instructions LGDT and SGDT give access to the GDTR LLDT and SLDT give access to the LDTR. Faculty Development Programme, SPP University, Pune

Selectors The selector portion of a logical address identifies a descriptor by specifying a descriptor table and indexing a descriptor within that table. Visual part of Segment register Selectors may be visible to applications programs as a field within a pointer variable Faculty Development Programme, SPP University, Pune

Fields of selector Index: Selects one of 8192 descriptors in a descriptor table. The processor simply multiplies this index value by 8 and adds the result to the base address of the descriptor table in order to access the appropriate segment descriptor in the table. Table Indicator: Specifies to which descriptor table the selector refers. A set=0, indicates the GDT. A set=1, current LDT Faculty Development Programme, SPP University, Pune

Selector Requested Privilege Level (RPL) Used by the protection mechanism. The first entry of the GDT is not used by the processor. A selector that points to the first entry of the GDT, can be used as a null selector. The processor does not cause an exception when a segment register (other than CS or SS) is loaded with a null selector. Faculty Development Programme, SPP University, Pune

Segment Registers (16 bit selector + Hidden)
The stores information from descriptors in segment registers, thereby avoiding the need to consult a descriptor table every time it accesses memory. Every segment register has a "visible" portion and an "invisible" portion. Faculty Development Programme, SPP University, Pune

Segment Registers The visible portions of these segment address registers are manipulated by programs as if they were simply 16-bit registers. The invisible portions are manipulated by the processor. The operations that load these registers are normal program instructions. These instructions are of two classes: 1. Direct load instructions; for example, MOV, POP, LDS, LSS, LGS, LFS. These instructions explicitly reference the segment registers. Faculty Development Programme, SPP University, Pune

Segment Registers 2. Implied load instructions; for example, far CALL and JMP. These instructions implicitly reference the CS register, and load it with a new value. Using these instructions, a program loads the visible part of the segment register with a 16-bit selector. The processor automatically fetches the base address, limit, type, and other information from a descriptor table and loads them into the invisible part of the segment register. Faculty Development Programme, SPP University, Pune

PAGE TRANSLATION In the second phase of address transformation, the transforms a linear address into a physical address. This phase of address transformation implements the basic features needed for page-oriented virtual-memory systems and page-level protection. The page-translation step is optional. Page translation is in effect only when the PG=1 bit of CRO is set. This bit is typically set by the operating system during software initialization. Faculty Development Programme, SPP University, Pune

PAGE TRANSLATION The PG bit must be set if the operating system is to implement multiple virtual 8086 tasks, page-oriented protection, or page-oriented virtual memory. A page frame is a 4K-byte unit of contiguous addresses of physical memory. Pages begin on 4K - byte boundaries and are fixed in size. Faculty Development Programme, SPP University, Pune

Linear Address A linear address refers indirectly to a physical address by specifying a page table, a page within that table, and an offset within that page. The processor converts the DIR, PAGE, and OFFSET fields of a linear address into the physical address by consulting two levels of page tables. Faculty Development Programme, SPP University, Pune

Linear address into the physical address
The addressing mechanism uses DIR field as an index into a page directory. PAGE field as an index into the page table determined by the page directory. OFFSET field to address a byte within the page determined by the page table. Faculty Development Programme, SPP University, Pune

Page Tables A page table is simply an array of 32-bit page specifier. Two levels of tables are used to address a page of memory. At the higher level is a page directory. The page directory addresses up to 1 K page tables of the second level. A page table of the second level addresses up to 1K pages. All the tables addressed by one page directory, therefore, can address 1M pages. Because each page contains 4 Kbytes 2^12 bytes), the tables of one page directory can span the entire physical address space of the (2^20 times 2^12 = 2^32). Faculty Development Programme, SPP University, Pune

Descriptor Faculty Development Programme, SPP University, Pune

Granularity (G) bit (G = 0) the 20-bit limit field is assumed to be measured in units of 1byte and (G = 1), the limit field is in units of 4KB Default size (D)-bit D = 0, operands contained within this segment are is 16 bits in size. D = 1, operands are assumed to be 32-bits. The AVL (available) describe descriptor is available for user or it is for use by operating system. Av=0: used by OS Av=1: available for user Faculty Development Programme, SPP University, Pune

Example of D bit uses for Code segment D = 0 means 16-bit code D = 1 means 32-bit code for Stack Segment D = 0  stack operations are 16-bit wide, SP is used as a stack pointer, maximum stack size is FFFF (64 KB) D = 1  stack operations are 32-bit wide, ESP is used as a stack pointer, maximum stack size is FFFFFFFF (4GB) Faculty Development Programme, SPP University, Pune

Types of descriptors The has five types of descriptors listed as follows: 1.Code or Data Segment Descriptors. 2.System Descriptors. 3.Local descriptors. 4.TSS (Task State Segment) Descriptors. 5.GATE Descriptors. The provides a four level protection mechanism exactly in the same way as the does. Faculty Development Programme, SPP University, Pune

Descriptors Faculty Development Programme, SPP University, Pune

APPLICATIONS INSTRUCTION SET
To write application software for the executing in protected virtual-address mode. DATA MOVEMENT INSTRUCTIONS They fall into the following classes: 1. General-purpose data movement instructions. 2. Stack manipulation instructions. 3. Type-conversion instructions. Faculty Development Programme, SPP University, Pune

General-Purpose Data Movement Instructions
MOV (Move) transfers a byte, word, or double word from the source operand to the destination operand. The MOV instruction is useful for transferring data along any of these paths • To a register from memory • To memory from a register • Between general registers • Immediate data to a register • Immediate data to a memory XCHG (Exchange) swaps the contents of two operands. Faculty Development Programme, SPP University, Pune

Stack Manipulation Instructions
PUSH (Push) decrements the stack pointer (ESP), then transfers the source operand to the top of stack indicated by ESP PUSH is often used to place parameters on the stack before calling a procedure. The PUSH instruction operates on memory operands, immediate operands, and register . PUSHA (Push All Registers) saves the contents of the eight general registers on the stack.. The processor pushes the general registers on the stack in the following order: EAX, ECX, EDX, EBX, the initial value of ESP before EAX was pushed, EBP, ESI, and EDI. Faculty Development Programme, SPP University, Pune

Type Conversion Instructions
The type conversion instructions convert bytes into words, words into double words, and double words into 64-bit items (quad-words). CWD, CDQ, CBW, and CWDE CWD (Convert Word to Doubleword) CBW (Convert Byte to Word) CDQ (Convert Doubleword to Quad-Word) CWDE (Convert Word to Doubleword Extended) MOVSX (Move with Sign Extension) MOVZX (Move with Zero Extension) Faculty Development Programme, SPP University, Pune

BINARY ARITHMETIC INSTRUCTIONS
ADD, ADC, INC, AAA, and DAA CMP (Compare) MUL (Unsigned Integer Multiply) IMUL (Signed Integer Multiply) DIV (Unsigned Integer Divide) IDIV (Signed Integer Divide) DAA (Decimal Adjust after Addition) DAS (Decimal Adjust after Subtraction) Faculty Development Programme, SPP University, Pune

LOGICAL INSTRUCTIONS The group of logical instructions includes: NOT (Not) AND, OR, and XOR • The Boolean operation instructions • Bit test and modify instructions • Bit scan instructions • Rotate and shift instructions • Byte set on condition Faculty Development Programme, SPP University, Pune

Shift and Rotate Instructions
These instructions fall into the following classes: • Shift instructions • Double shift instructions • Rotate instructions Faculty Development Programme, SPP University, Pune

SHIFT INSTRUCTIONS The bits in bytes, words, and double words may be shifted arithmetically or logically. CF always contains the value of the last bit shifted out of the destination operand. OF is set if the value of the high-order (sign) bit was changed by the operation. SAL (Shift Arithmetic Left) SHL (Shift Logical Left) SHR (Shift Logical Right) SAR (Shift Arithmetic Right) ROL (Rotate Left) ROR (Rotate Right) RCL (Rotate Through Carry Left) Faculty Development Programme, SPP University, Pune

SAL/SHL SAL (Shift Arithmetic Left) shifts the destination byte, word, or double word operand left by one or by the number of bits specified in the count operand The processor shifts zeros in from the right (low-order) side of the operand as bits exit from the left (high-order) side. Sal AX,CL Faculty Development Programme, SPP University, Pune

SHR (Shift Logical Right)

SAR (Shift Arithmetic Right)
The processor preserves the sign of the operand by shifting in 0 on the left (high-order) side if the value is positive or by shifting by 1 if the value is negative. SAR is rounded toward negative infinity Faculty Development Programme, SPP University, Pune

DOUBLE-SHIFT INSTRUCTIONS
These instructions provide the basic operations needed to implement operations on long unaligned bit strings. The double shifts operate either on word or double word operands, as follows: SHLD (Shift Left Double) :shifts bits of the R/M field to the left, while shifting high-order bits from the Reg field into the R/M field on the right. The result is stored back into the R/M operand. The Reg field is not modified. Faculty Development Programme, SPP University, Pune

SHRD (Shift Right Double) shifts bits of the RIM field to the right, while shifting low-order bits from the Reg field into the RIM field on the left Faculty Development Programme, SPP University, Pune

ROTATE INSTRUCTIONS Rotate instructions allow bits in bytes, words, and double words to be rotated. Bits rotated out of an operand are not lost as in a shift, but are "circled" back into the other "end" of the operand. Rotates affect only the carry and overflow flags. CF may act as an extension of the operand. CF always contains the value of the last bit rotated out. Faculty Development Programme, SPP University, Pune

ROL and ROR ROL (Rotate Left) rotates the byte, word, or double word destination operand left by one or by the number of bits specified in the count operand . Faculty Development Programme, SPP University, Pune

RCL and RCR It treats CF as a high-order one-bit extension of the destination operand. Faculty Development Programme, SPP University, Pune

CONTROL TRANSFER INSTRUCTIONS
Unconditional Transfer Instructions: JMP, CALL, RET, INT and IRET Faculty Development Programme, SPP University, Pune

Conditional Transfer Instructions:

Conditional LOOPE (Loop While Equal) and LOOPZ (Loop While Zero) LOOPNE (Loop While Not Equal) and LOOPNZ (Loop While Not Zero) Faculty Development Programme, SPP University, Pune

STRING AND CHARACTER TRANSLATION INSTRUCTIONS
1. A set of primitive string operations MOVS — Move String CMPS — Compare string SCAS — Scan string LODS — Load string STOS — Store string 2. Indirect, indexed addressing, with automatic incrementing or decrementing of the indexes. Indexes: ESI —- Source index register EDI — Destination index register Control flag: DF — Direction flag Control flag instructions: CLD Clear direction flag instruction STD — Set direction flag instruction 3. Repeat prefixes REP Repeat while ECX not zero REPE/REPZ Repeat while equal or zero REPNE/REPNZ Repeat while not equal or not zero Faculty Development Programme, SPP University, Pune

FLAG CONTROL INSTRUCTIONS
Effect STC (Set Carry Flag) CF <- 1 CLC (Clear Carry Flag) CF <- O CMC (Complement Carry Flag) CF <- NOT (CF) CLD (Clear Direction Flag) DF <- O STD (Set Direction Flag) DF <- 1 Faculty Development Programme, SPP University, Pune

COPROCESSOR INTERFACE INSTRUCTIONS
The also has features to support emulation of the numeric coprocessor when the coprocessor is absent. ESC (Escape) : Used by Coprocessor is a 5-bit sequence that begins the opcodes that identify floating point numeric instructions. ESC: numeric coprocessor tells the to send the opcode and addresses of operands to it The numeric coprocessor uses the escape instructions to perform high-performance, high-precision floating point arithmetic. Faculty Development Programme, SPP University, Pune

COPROCESSOR INTERFACE INSTRUCTIONS
WAIT (Wait) suspends (80386) program execution until the CPU detects that the BUSY pin is inactive. This condition indicates that the coprocessor has completed its processing. Faculty Development Programme, SPP University, Pune

SEGMENT REGISTER INSTRUCTIONS (In Groups)
Segment-register transfer instructions. MoV ••• , SegReg PUSH SegReg POP SegReg Control transfers to another executable segment.: JMP far CALL far RET far Data pointer instructions. LOS LES LFS LGS LSS Faculty Development Programme, SPP University, Pune

Data Pointer Instructions
LDS (Load Pointer Using DS) LES (Load Pointer Using ES) LFS (Load Pointer Using FS) LGS (Load Pointer Using GS) LSS (Load Pointer Using SS) Other LEA (Load Effective Address) NOP (No Operation) XLAT (Translate) Faculty Development Programme, SPP University, Pune

EXCEPTIONS AND INTERRUPTS
Interrupts and exceptions are special kinds of control transfer; they work somewhat like un-programmed CALLs. They alter the normal program flow to handle external events or to report errors or exceptional conditions Interrupts are used to handle asynchronous events external to the processor. Exceptions handle conditions detected by the processor itself in the course of executing instructions. Faculty Development Programme, SPP University, Pune

EXCEPTIONS AND INTERRUPTS
There are two sources for external interrupts and two sources for exceptions: 1. Interrupts • Maskable interrupts, which are signalled via the INTR pin. •Non-maskable interrupts, which are signalled via the NMI (Non-Maskable Interrupt) pin. 2. Exceptions or software interrupts • Processor detected. These are further classified as faults, traps, and aborts. • Programmed. The instructions INTO, INT 3, INT n, and BOUND can trigger exceptions. Faculty Development Programme, SPP University, Pune

Interrupt and Exception ID Assignments
0-32 type: The NMI and the exceptions recognized by the processor. 32-255: Maskable interrupts are determined by external interrupt controllers (Intel's 8259A Programmable Interrupt Controller) and communicated to the processor. Faculty Development Programme, SPP University, Pune

Interrupt and Exception ID Assignments

Types of Exceptions 1.Faults: Faults reported "before" the instruction causing the exception. Faults are either detected before the instruction begins to execute, or during execution of the instruction. If detected during the instruction, the fault is reported with the machine restored. 2.Traps A trap is reported at the instruction boundary immediately after the instruction in which the exception was detected. Faculty Development Programme, SPP University, Pune

Types of Exceptions 3.Aborts Permits neither precise location of the instruction causing the exception nor restart of the program that caused the exception. Aborts are used to report severe errors, such as hardware errors and inconsistent or illegal values in system tables. Faculty Development Programme, SPP University, Pune

Priority Among Simultaneous Interrupts and Exceptions

ENABLING AND DISABLING INTERRUPTS
Certain conditions and flag settings cause the processor to inhibit certain interrupts and exceptions. NMI Masks Further NMls: processor ignores further interrupt signals at the NMI pin until the next IRET instruction is executed. IF (9 bit) Masks INTR: When IF=O, INTR interrupts are inhibited (disable). When IF=I, INTR interrupts are enabled. Processor clears IF in response to a RESET signal. The instructions CLI and STI alter the setting of IF (if CPL <=IOPL, otherwise exception). RF Masks Debug Faults: Faculty Development Programme, SPP University, Pune

INTERRUPT DESCRIPTOR TABLE
The interrupt descriptor table (IDT): Associates each interrupt or exception identifier with a descriptor for the instructions that service the associated event. Like the GDT and LDTs, the IDT is an array of 8-byte descriptors. Unlike the GDT and LDTs, the first entry of the IDT may contain a descriptor. To form an index into the IDT, the processor multiplies the interrupt or exception identifier by eight. IDT need not contain more than 256 descriptors. Faculty Development Programme, SPP University, Pune

Working The IDT may reside anywhere in physical memory. Processor locates the IDT by means of the IDT register (IDTR). The instructions LIDT and SlDT operate on the IDTR. Faculty Development Programme, SPP University, Pune

Important Instruction
LIDT (Load IDT register) (CPL=0): Loads the lDT register with the linear base address and limit values contained in the memory operand. SIDT (Store IDT register): execute at any level): copies the base and limit value stored in IDTR to a memory location. Faculty Development Programme, SPP University, Pune

lDT DESCRIPTORS The IDT may contain any of three kinds of descriptor: • Task gates: can handle task • Interrupt gates: handle interrupt procedure • Trap gates: Handle trap procedure Interrupt / exception are just as CALL (using call gate). Faculty Development Programme, SPP University, Pune

Differences Task/Interrupt/ Trap

INTERRUPT TASKS AND INTERRUPT PROCEDURES
Gate call indirectly to procedure in LDT / GDT Faculty Development Programme, SPP University, Pune

STACK OF INTERRUPT PROCEDURE
Interrupt or exception handling procedure uses the stack to store the information needed for returning to the original procedure as CALL. IRET for returning. Faculty Development Programme, SPP University, Pune

Summary of Interrupt Faculty Development Programme, SPP University, Pune

Thanks Faculty Development Programme, SPP University, Pune

80386DX-Basic Programming Model and Applications Instruction Set

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