Advanced Digital Design

Advanced Digital Design
Asynchronous Design: Bundled Data A. Steininger Vienna University of Technology

© A. Steininger / TU Vienna
recall Previous Conclusion The purpose of a design style is to provide information for flow control. Boolean Logic alone cannot provide this information. Severe technological problems force us to question the current (synchronous) design practice. We shall focus on that. Alternatives must be evaluated very critically with respect to improvements concerning power, area, robustness, ease of composition, testability and performance. Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

recall Our Options We must only use consistent input vectors How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

Outline The Handshake Principle Sutherland‘s Micropipeline Transition Signaling The Bounded Delay Approach Capture & Issue Condition Other Delay Models Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Handshake Principle REQ: „Data word valid, you can use it“ When can SNK use its input? When it is valid and consistent f(x) SRC SNK When can SRC apply the next input? When SNK has consumed the previous one ACK: „Data word consumed, send the next“ Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

Asynchronous Philosophy
„The control flow requires agreement between source and sink. For this purpose they need to communicate“ Source indicates capture condition for sink. Sink indicates issue condition for source. „HANDSHAKE“ Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Real-life comparison Synchronous systems: train airplane school,… Handshake-like systems: family departure with car discussion catching a fish Why these different schemes? Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Push Channel REQ: „Data word valid, you can use it“ initiates hand-shake 1 f(x) SRC SNK 2 ACK: „Data word consumed, send the next“ Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Pull Channel REQ: „Send a new data word“ 1 initiates hand-shake f(x) SRC SNK 2 ACK: „Here it is“ Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

2 Phase vs. 4 Phase 2 phase protocol (NRZ): 4 phase protocol (RTZ) 1 1 REQ REQ 2 2 ACK ACK 1 3 1 3 REQ REQ 2 4 2 4 ACK ACK Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Data Validity – 2 Phase Source: [Sparso 06] Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Data Validity – 4 Phase push channel Source: [Sparso 06] REQ determines start, ACK end of validity Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Data Validity – 4 Phase pull channel Source: [Sparso 06] ACK determines start, REQ end of validity Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Micropipeline: Principle
ACKn REQn-1 ACKn+1 C C REQn f(x) L1 L2 En En capture „bundled data“ (handshake performed for „bundle“ of data) Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

A very Important Detail
The handshake establishes a closed-loop control for the data flow between sender and receiver This makes operation more robust than in the synchronous (= open-loop) case The art of asynchronous design is to make these closed loops interoperate properly This is much more complicated than a synchronous design. Time is continuous now, no more discrete Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

The Indication Principle
a sender will not produce a new output before it received an ACK from all receivers every transition is confirmed this principle enforces the issue condition makes the timing adaptive (closed loop) makes fault tolerance cumbersome (wait forever for failed receiver…) needs to be considered in the design of asynchronous circuits: no „dead ends“ no „unauthorized inputs“ Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Micropipe: Capturing capture data if predecessor has new data available (REQn-1) and successor is ready to accept new data (ACKn+1) produce  at capture (output) after  of REQ and  of ACK Muller C-Element REQn-1 ACKn+1 C Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline „FIFO for transitions“ C RIN AOUT AIN ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline initial state C C RIN AOUT AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline request (rising edge) C C RIN AOUT AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline request passes stage 1 C C RIN AOUT AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline request passes stage 2 C C RIN AOUT AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline request passes stage 3 => output C C RIN AOUT AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline further request (falling edge) C C RIN AOUT AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline new request passes stage 1 C C RIN AOUT AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline new request passes stage 2 C C RIN AOUT AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline new request blocked for stage 3 C C RIN AOUT Req 1 remains „stored“ AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline one more request … C C RIN AOUT AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline … passes stage 1 only … C C RIN AOUT AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline ... ands remains stored there C C RIN AOUT Req 3 stored here Req 2 stored here Req 1 stored here AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline acknowledge from output (rising edge) C C RIN AOUT Req 3 Req 2 Req 1 AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline ack passes stage 3 C C RIN AOUT AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline stage 2 is now free for… C C RIN AOUT Req 3 Req 2 AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline … request from stage 1 C C RIN AOUT Req 3 Req 2 AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline new ack (falling edge) … C C RIN AOUT Req 3 Req 2 AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline ... allows remaining request to move up to stage 3 C C RIN AOUT Req 3 AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Elastic Pipeline ready for new req or ack C C RIN AOUT Req 3 AIN C ROUT Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Adding a Data Path RIN C C AOUT AIN ROUT C Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

Adding a Data Path RIN C C AOUT c pD cD p c pD cD p c pD cD p AIN ROUT C Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Capture/Pass Register
must react to both edges („two phase handshake“) has dedicated input for both, „capture“ and „pass“ has delayed output for both control inputs („capture done“, „pass done“) to make sure capture occurs before „capture done“ is output c pD cD p Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

C/P Reg: Implementation
Source: [Sparso 06] Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Using Simple Latches RIN C C AOUT En En En AIN ROUT C What‘s the difference to before? Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

Adding Computations RIN C C AOUT En En En AIN ROUT C Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

The need for a delay REQ: „Data word valid, you can use it“ event = issue of data word ! race condition ! f(x) SRC SNK ACK: „Data word consumed, send the next“ event = latching of data word safe (?) Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

Example: Centronix Data „REQ“ „ACK“ [Centronix Spec for ETRAX100LX, „Fastbyte Mode“] Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Criticality of ACK f(x) L2 SRC SNK „capture!“ cannot measure „act of capturing“ as an event use „capture!“ command instead in addition, fork produces race between trigger edge and next data wave race is uncritical (but still exists!) Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

Bounded Delay approach
TRGSNK (REQ) tSRC tSNK SRC SNK TRGSRC (ACK) coordinate SNK & SRC by a handshake still requires delays: SRC delays issuing sink trigger (REQ) SNK delays issuing source trigger (ACK) Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

recall The Issue Condition tSNK Control TRGSRC: Have SRC issue the next data word such that the current one can still be safely consumed by SNK. Formal Condition: tinvalid,x > tsafe,x msrc > - Dinvalid Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

Bundled Data: Issue Cond.
Delay source trigger by tsnk = Dsnktrg + Dcons+ msrc This is the delay between „capture“ and „capture done“ in the micropipeline. For tsnk = 0 we end up like in the synchronous case: msrc = -(Dsnktrg + Dcons) this is not safe, but works, as long as Dinvalid > Dsnktrg + Dcons SRC actually triggers SNK, no synchrony assumptions! Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Criticality of REQ f(x) SRC SNK cannot use issue trigger as an event: produces unacceptable race between data and REQ must introduce timer (bounded delay) Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

recall The Capture Condition tSRC Control TRGSNK: Have SNK capture data only after it has become consistent. Formal Condition: tcons,x > tsnkrdy,x msnk > - Dsnktrg Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

Bundled Data: Capture Cond.
Delay source trigger by tsrc = Dsrc + Dproc + Dsnk + msnk This definitely requires a delay element. Like in the synchronous case we end up estimating the involved delays Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Drawback of the delay the skew problem still exists (!) need to determine suitable value for D need to make worst case assumptions for determination of D does not work without constraints on the individual path delays „Bounded Delay Model“ Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Gain of Bounded Delay timer settings need to determine clock period circuit functionality is technology dependent considerable design efforts, large design loops need to make worst-case assumptions necessarily pessimistic no robustness wrt. exceeding them need to maintain global synchrony clock distribution problems power consumption problems  Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

Bundled Data at a Glance
single-rail data coding 4- or 2-phase handshake Source: [Sparso 06] Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

The Ideal Case asynchronous approach: TRGsrc TRGsnk tCO valid ACK TRGsrc completion detection ACK tCO tpd valid REQ delay REQ  Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

The Ideal Case asynchronous approach: TRGsrc tCO valid TRGsrc completion detection ACK tCO tpd ACK valid ACK delay REQ  TRGsnk Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

The Ideal Case asynchronous approach: REQ completion detection TRGsrc TRGsnk tCO valid ACK TRGsrc ACK tCO tpd alid data delay  Does not work for Bounded Delay Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

recall Criticality of REQ f(x) SRC SNK cannot use issue trigger as an event: produces unacceptable race between data and REQ must introduce timer (bounded delay) OR: find better event (downstream) completion detection Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

Current Sensing: Idea Transitions on data rails cause dynamic current In the absence of dynamic current data must be stable current sensor can be used for completion detection Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Current Sensing: Problems
inversion of causality is not safe: What if bit changes after circuit has been considered stable? What if no bit changes? same data word transmitted again leakage dominates – proportion of dynamic current is decreasing current sensor is undesired analog circuitry Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Delay Models synchronous model known bounds for delays, global timing bounded delay model (BD, fundamental) known bounds for absolute delays, local timing scalable-delay-insensitive model (SDI) bounds for relative deviation between delays known quasi-delay-insensitive (QDI) output paths of a fork have same delay delay insensitive (DI) no restrictions on delays (just finite) syn: optimistisch, immer schwieriger zu erfüllen Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Speed Independence Source: [Sparso 06] gates: dA, dB, dC arbitrary (bounded); wires: d1=d2=d3=0 idea: neglect wires, consider gate delays only in practice: unrealistic, since wire delay is not negligible sometimes useful to simplify modeling Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Definition of SI a gate is stable if current ouput suits to current inputs excited if output needs to change to follow recent change of inputs firing when this change happens assume an excited gate A‘s input sourced by another excited gate B that fires first then A may remain excited or B‘s firing may change A‘s input so as to cancel A‘ excitation (b) indicates a hazard the circuit is SI if (b) can never happen Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

recall Static Comb. Hazard Fundamental circuit structure: (static 0 hazard) A rising transition on A will excite both gates, if INV fires first it will cancel the AND gate‘s excitation Y = A  A  0 A Lecture "Advanced Digital Design" © A. Steininger / TU Vienna *

Quasi-Delay-Insensitive
Source: [Sparso 06] gates: dA, dB, dC, wires: d1, d2 arbitrary; d3=d2 („isochronic“ fork) idea: now both wire paths have same delay => can be summed up with dA and considered part of gate delay in practice: isochronic forks can be realized in basic blocks by careful routing Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Delay-Insensitive Source: [Sparso 06] gates: dA, dB, dC arbitrary (bounded) wires: d1, d2, d3 arbitrary (bounded) idea: no assumptions, unrestricted timing behavior in practice: very limited choice of functions (see later) valid abstraction in in high level design with basic blocks Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

The limits of true DI generalized structure of asyn circuit: A‘s logic A X G shared logic B B‘s logic single-output gate G with at least 2 inputs (A, B) need feedback for all inputs => FORK (control loop) if G fires upon receipt of 1st feedback (say A) => other path (B) gets out of sync => hazard => G needs to wait for transitions on all its inputs => can only use Muller C-gate and INV but not AND, OR, … Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Model Overview Source: [Sparso 06] speed-independent: dA, dB, dC arbitrary; d1=d2=d3=0 delay-insensitive: dA, dB, dC, d1, d2, d3 arbitrary quasi-delay-insensitive: dA, dB, dC, d1, d2 arbitrary; d3=d2 (minimum requirement to allow AND, OR etc.) self-timed: other general word for „asynchronous“ Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Bundled Data: Model? Control path (Muller pipeline) is DI only uses Muller C-gate and inverter needs glitch-free implementation works without delay assumptions Data path uses bounded delay model can use all types of gates can allow glitches must know all absolute delays with „matched“ delay element can use SDI Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Conclusion (1) Alternatively to a global time base a handshake can establish the required synchronization between source and sink: The source issues a REQ to signal that new data are valid, and the sink issues ACK when it is ready for the next data. In principle the handshake can establish a closed control loop for data flow, which yields higher robustness but variable timing. Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Conclusion (2) The micropipeline is the basic approach for structuring asynchronous circuits. It couples individual source/sink pairs The bundled data approach utilizes the micropipeline for controlling latches (of different style) that form a data path. The forward delay by the computation blocks is countered by matched delay elements. This requires knowledge of all involved delays, thus spoiling the flexibility Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

Conclusion (3) There are different timing models bounded delay scalable-delay-insensitive quasi-delay-insensitive delay insensitive they allow buying design efficiency by making timing assumptions Lecture "Advanced Digital Design" © A. Steininger / TU Vienna

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