1. EFW Instrument Testing to date
Michael Ludlam for EFW Team
Space Sciences Laboratory
University of California, Berkeley

2. Overview IDPU Board Testing Boom Qualification Instrument Testing
DCB & FSW
LVPS
BEB
DFB
Boom Qualification
AXB
SPB
Instrument Testing
IDPU Integration
Boom Deployments
AC Test / BEB sensor control
Noise, Timing, Phasing
Calibration

3. DCB Testing
Both FM DCB boards have completed & passed their board functional test – (RBSP_EFW_DCB_009)
Boards have been integrated into IDPU and function correctly with other boards and booms.
FSW v3.00 burned into PROMs. Installed on boards. Initially some problems, but failure analysis is pointing towards lead bending procedure. New parts bent correctly both work on flight units. Limited thermal testing was conducted & passed to verify no thermal issues.
Other DCB modifications
Flash FET switches layout reversed. Rework fix.
Addition of inductor to suppress SEE induced transients from MSK regulators.
Flight board termination was different than ETU requiring a number of resistor changes.

4. DCB Photo

5. FSW Status
FSW complete. Burned in PROMs after completion of CPT on ETU.
All Analyses completed : RBSP_EFW_FSW_004_Analyses.xls
Comprehensive Test Report : RBSP_EFW_FSW_020C_CPT_ pdf
Code Inspection Report : RBSP_EFW_FSW_021_Inspection.pdf
Long Duration Stress Test Report : RBSP_EFW_FSW_022B_LDS_Report.pdf

6. Summary FSW Development On-Board Scripts
PROM Software Contains all Required Functions
EEPROM is empty at this point
On-Board Scripts
Room Available in PROM
No Scripts Defined
Verification at the Box & Instrument levels (Not FSW-level)
GSE/SOC Flash Memory “MET-to-Block” data management
Boom Door Opening & Wire Deployment
Real Data Compression (Requires Signals In, SOC to decode)
EEPROM test in TVAC

7. RBSP LVPS Testing
LVPS Testing completed on both boards. All functions passed.
LVPS Testing is divided into sections
5- Floaters
Output Voltage Range
Load tests
Output Ripple Measurement
Line Voltage Test
Short Circuit Protection Test
SYNC test
Verified that all sections are operating at 200KHz when the internal clock is activated
Verified that when an external Clock is applied all sections are synchronized
Verified that internal crystal is turned off when an external clock is applied
Housekeeping
Inrush Current
40V Survival test
1- BEB Digital and Analog
2- IDPU Digital
3- IDPU Analog
4- BEB 225V
These four sections have the same topology. The following tests were performed to verify their function individually:
Frequency Adjustment to 187KHz
FET Gate and Drain Waveform Check
Verify Output Voltages
Load Test (half load/ full load/no load)
Output Ripple Measurement
Line Test where S/C Voltage is varied from 24V to 35V
Short Circuit Protection Test where a 1 Ohm resistor load is applied and the circuit recovers from this large load.

8. RBSP LVPS testing Power Control Board Testing
Reference Voltage is verified
Housekeeping Monitor values are verified.
Motors, Doors and Stacers Activation verified using a tester that consists of resistors and LEDs
Each command was sent separately and the current consumption is recorded.

9. LVPS Photo

10. All Digital Fields Boards Delivered
All 3 DFBs delivered to Berkeley
All tested and qualified for flight
DFBs meet or exceed all performance requirements
No known performance deficiencies

11. DFB Entrance Criteria – All Met
All Requirements Verified
Release/signature process complete
All RFAs closed
Deviation or Waivers
Completing release/signature process on 1 remaining waiver for PCB bake-out recording. CCB approved 1/3/11.
One Part issue in resolution
Op-Amp failure analysis in process by APL
End-Item-Data Packages completing
FM-1 complete and delivered to Berkeley
FM-2 & FM-3 waiting on outstanding waiver
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12. Extensive Testing on all DFBs
All board-level testing complete on all DFBs per the test plan
Tested the full default configuration of each DFB
Science data products including: Survey and Burst data from the digital filters, Trigger data, Spectral data, and Cross spectral data
Synch to 1 PPS test, super-synch (long and 1sec)
Full Analog section testing - 16K ADC sampling
Stimulated analog inputs create proper response on the appropriate digital outputs
Verified that each digital data product can access all its commandable sources.
Obtained calibration data
Gains, Offsets, Crosstalk and Noise Characteristics
Long duration testing ran on each board 3-4 days each
Thermal cycle testing between -25 to +55 on all DFBs
No open work remaining on any DFB

13. DFB Tests Performed Register Read Test Spectral Dynamic Enable Test
Spectral IDL Compare
Cross-Talk Test
Full Default Test
Spectral Bins Test
Cross-Spectral IDL Compare
Noise Test
ADC MUX Switching Test
Cross-Spectral Bins Test
FAP Initial Functionality Test
Gain Test
Waveform Verify Channel Test
Spectral Dynamic Bins Test
Spectral FAP Test
Thermal Test
Trigger Vavg Test
Spectral Cycle Ncad Test
Super-synch Test I
Power Draw
Waveform Maximum Bandwidth Test
Cross-spectral Cycle Ncad Test
Super-synch Test II
FAP IDL Comparison
Spectral Bandwidth Test
Spectral Dynamic Ncad and Navg Test
Trigger Frequency Response Test
Invalid Configurations Test
Trigger Cycle Sources Test
Triggers Speed Select Test
Waveform Frequency Response Test
Digital Filter Delays
Spectral Cycle Sources Test
Waveform IDL Compare Test
AC Common Mode Rejection Test
Frequency Response Testing
Cross-Spectral Cycle Sources Test
Trigger IDL Compare Test
DC Common Mode Rejection Test
Signal Integrity and Timing Tests

14. BEB Testing
The following tests were performed during bench testing of the BEB.
DC offset Test
DAC and MUX Setting Verification test
DC Gain Verification
Frequency Response Verification
EMFISIS Distortion Test
EMFISIS Frequency Response
AC Test Line Verification

15. BEB Example Results
All measurements were in specification. More details in Calibration slides.
Gain
Frequency (Hz)

16. BEB Photo

17. Boom Qualification
All AXB and SPB units have completed qualification programme.

18. Axial Booms (AXB) Jeremy McCauley Spacecraft +Z Aerospace Engineer
Space Sciences Laboratory, UCB
Spacecraft +Z
AXB
AXB
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19. EFW AXB Environmental Testing
PER
Integrate Stacer, Whip and Cage
Electrical Functional Test
Integrated Vibration Test
Electrical Functional Test
Stacer Mech Functional, Length & Runout Measurement, Continuity Check
Whip and Cage Mechanical Functional
Electrical Functional Test
Dis-Integrate Stacer, Whip and Cage
Whip and Cage TV Hot Deploy
Whip and Cage TV Cold Deploy
Integrate Stacer, Whip and Cage
Mass Properties
Science Calibration
Stacer Mech TV Hot Deploy, Length & Runout Measurement, Continuity Check
Stacer Mech TV Hot Deploy, Length & Runout Measurement, Continuity Check
PSR
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20. EFW AXB I&T: Deployments
Functional Deployments
Expected number of deployments on the instrument at launch: 5
Functional (MIP)
Post Vibe Functional (“test as you fly” exception)
Thermal Vacuum Hot
Thermal Vacuum Cold
INT Deployment with IDPU and Flight Harness
Deployments of Whip and Cage
at SC Level after Vibe
All stacer deployments include:
Frangibolt and Motor trending,
EOT Switch verification,
Continuity verification,
Runout and
Stiffness testing.
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21. EFW AXB I&T: Alignment Alignment Testing
Runout Requirement: <1° from spin axis F1 F2
ETU
SN_004
SN_005
SN_003
SN_006
Runout [deg]:
0.49
0.92
0.61
0.55
Stiffness [lb/in]:
0.0040
0.0043
0.0036
0.0037
0.0033
Fundamental Frequency [Hz]:
0.23
0.26
0.27
0.25
FF Hanging [Hz]:
0.43
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22. EFW AXB I&T: Vibration Vibration Testing 121
Sine Vibration to flight levels per Section 5.4.5
Random to GEVS Workmanship Levels per Section 5.4.5
Self-shock survival from boom deployment actuations
ETU First Frequency: X, Y = 180 Hz, Z = 275 Hz
FM1 (SN_004) First Frequency: X, Y = 177 Hz, Z = 275 Hz
FM1 (SN_005) First Frequency: X, Y = 160 Hz, Z = 295 Hz
FM2 (SN_003) First Frequency: X, Y = 166 Hz, Z = 278 Hz
FM2 (SN_006) First Frequency: X, Y = 157 Hz, Z = 297 Hz
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23. Whip & Caging Mechanism
EFW AXB I&T: TV
Thermal Vacuum Testing
4(6) operational cycles plus 1 survival cycle, per the requirements and limits indicated in section 5.3.2
Deployment tests at hot and cold levels
HOT TURN ON
HOT DEPLOY N
COLD TURN ON
COLD DEPLOY
COMPONENT
OPERA-TIONAL MIN
OPERA-TIONAL MAX
SUR-VIVAL MIN
SUR-VIVAL MAX
Whip & Caging Mechanism
-25 65
-30 70
Deploy Mechanism 55 60
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24. EFW AXB Mass Properties Testing
Unit SN:
Mass: [kg]
MOI (X-X): [kg/m^2]
MOI (Y-Y): [kg/m^2]
MOI (Z-Z): [kg/m^2]
ETU
3.065
0.160
0.122
0.045
F1 SN_004
3.158
0.169
0.120
0.040
F1 SN_005
3.145
0.168
0.114
F2 SN_003
0.166
0.121
0.044
F2 SN_006
0.167
0.123
0.043
Mass: 2.97 predict, 3.40 NTE
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25. EFW AXB HYPOT Testing HYPOT Testing:
Connectors need testing for resistance to High Potential (HI POT)
Not reasonable on a part by part basis
Individual representative components passed
Harness tested in unit
Whip Hinge
Whip Harness
Sphere
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26. EFW AXB Status Harness Passed HyPot Testing
Mechanisms Passed Vibration
Mechanisms Passed Thermal Vacuum
Mass Properties Testing Completed
INT Deploys completed
SN_004 will be tested again with updated Frangibolt
AXB ready for INT Environments
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33. Instrument Testing Instrument Testing
All IDPU boards have been integrated into IDPU boxes. Functional testing mostly occurs at the instrument level. Most testing is to do with instrument performance.
Boom Deployments have been conducted with Flight IDPU/ Flight Boom Units on all booms.
AC Test / BEB sensor control tests complete.
Verification of HSK complete.
Noise, Timing, Phasing, ‘Full Up’, Calibration to be discussed by John Bonnell.

34. Backup Slides

35. FSW Overview Development Plan : RBSP_EFW_001_SMP
Heritage : CRRES, Polar, Cluster, THEMIS
Language: Z80
Requirements: 193 Level 3
Effort : SLOC in 22 modules & include files (596 pages)
Test Platform: ETU
Quality : Integrated with Flight Development
Major Functional Requirements:
Command Reception & Distribution
Real-Time Data Collection and Playback
On-Board Evaluation for Burst Triggering
Burst Data Collection and Playback
Sine-Wave Fits of E-Field & Mag Signals
Spacecraft Potential Calculation
Data Compression
Boom Deployment Control
Space Weather Packet
Backup EMFISIS Magnetometer

36. Commands and Telemetry
TM: bps
- RT: bps
PB: 5237 bps

37. CPU Utilization CPU Performance Based upon 16.8 MHz processor
Measurements made on RBSP ETU DCB
Calculations in RBSP_EFW_FSW_004_Analyses.xls
Using Worst Case Compressable Data (10:1 compression)
Nominal Spin Rate (12 seconds) for Spin Fits

38. Memory Resources PROM/EEPROM PROM Functions EEPROM/Uplink
EEPROM Load
Uplink Support
L&EO Functions
EEPROM/Uplink
One-Time Events
Test Programs
Initialization Params
Science Upgrades
RESOURCE NEEDS
48% PROM
49% RAM
0% EEPROM

39. Computer Resources

40. Action Items/Changes Status of Action Items Since CDR
AI-8 : Required Long Duration Stress Test
Completed 11/11/2009
Details in Backup Section
Requirements Changes Since CDR
EFW-206 : Updated default “old data” as 42 days not 17
DFB-21 : Added DCB-to-DFB Synchronization message
TM-8 : Real-time data increased from 6.2 to 6.7 kbps
: Playback reduced from 5.7 kbps to 5.2 kbps
: Meets “370 samples/sec” requirement w/ compression

41. RBSP Radiation Belt Storm Probes
Instrument Critical Design Review
Action Item 8
Peter R. Harvey
Radiation Belt Storm Probes
RBSP
Action : Stress & Long Duration FSW Tests
Description: Include a long duration as well as stress tests of FSW (maybe combined).
Originator: Maureen Bartholomew

42. Requirements of Test Test Requirements Length : 72 Hours Activities :
High Rate of Commands
High Rate of Telemetry
Include Event Messages
Include Memory Dumps
Include CPU intensive Processing
Pass/Fail Criteria :
No Errors
No Memory Leaks

43. Long Duration Stress Test
High Rate of Commands
Command Pass Simulation Every Hour
Memory Load – Uplink of Script Database (1KB)
Serial Commands – 32 commands/sec for 60 seconds
Memory Dump Script Database
Execute Script and Verify Results
High Rate of Telemetry
Continuous Telemetry at 200% nominal (24 Kbps)
Real Time 200% (12 Kbps)
Burst 200% (12 Kbps)
CPU Intensive Processing
Spin Fit 200% (6 second period)
Spacecraft 200% (6 second period)
Burst Triggers (All 6 formulae active w/ 10 terms ea) (200% nominal)
Bias Sweeps every 30 minutes, Highest Frequency Possible
Data Compression Enabled on All Packets
SDRAM and SRAM Memory Scrubbing Enabled
Verification
Test Status Logged Every Hour (72 reports)
No Errors in FSW or GSE
No Memory Leaks (by design, there is no dynamic memory allocation)

44. RBSP EFW LVPS LVPS Problem Failure Reports Problem Failure Reports
There were 8 PFRs and 15 Engineering Change Notices.
Problem Failure Reports
PFR 022: IC leads were cut to fit the pads. MRB approved
PFR 025: L4, L7 have pads that are too small for the magnetic wire. The wires are connected to the leads of capacitors. MRB approved
PFR 038: Floater Magnetics assembly error. The magnetic wire was connected to a via. No damage occurred. FM1 only. MRB approved
PFR 030: Floater Voltages were out of range. Magnetics are re-wound using ‘balanced winding’. ECN 047 is generated. MRB approved.
PFR 037: C59 reversed capacitor. No damage occurs. The capacitor is replaced. FM1 only. MRB approved.
PFR 040: Adjusting IDPU Analog Output Voltages. ECN 045 is generated. MRB approved.
PFR 049: On board crystal did not turn off when the external clock from DCB is applied. ECN 056 is generated. Added a diode in the SYNC circuit. MRB approved.
PFR 055: When an external clock is applied to LVPS the signal looked distorted. Changing the feedback transformer ratio fixed this distortion. As precaution we changed U30 (NOR gate IC). FM2 was fixed before turn on. U30 is not replaced on FM2. ECN 060 is generated.
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45. RBSP EFW LVPS Engineering Change Notices LVPS ECNs
In order to capture BOM changes that did not cause any Problem Failure Reports we generated ECNs. Previous slide mentioned the ECNs that were generated for specific PFRs.
LVPS ECNs
ECN 046: Changing the voltage housekeeping resistor dividers to have 2.0V at the output
ECN 054: Added 1K resistors between grounds per systems request
ECN 055: Assigning MSK resistor and capacitor values post systems tests. These were TBD items before.
ECN 057: Changing a resistor value to match ETU.
ECN 061: Decreasing BEB Digital output voltage. When an external clock is applied BEB digital output voltage increases. Systems decided that if it is easy to decrease the output voltage then it is better to have voltage less than 5.35V.
ECN 062: During Derating Analysis we found a 50V ceramic capacitor. It is changed to a 100V ceramic capacitor.
ECN 063: Requirements change on 3.6V Digital output. Increase 3.6V digital output voltage per systems engineering request.

46. DFB Changes Since CDR Requirements Clarifications
Added SuperPPS for synching low rate data
FPGA Resource Constraints
Removed Solitary Wave Detector
Reduce spectral channels from 8 to 7
All science requirements still met
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47. DFB Waivers and Deviations status
Doc #
Type
Date
Subject
LASP
Project
115336
Deviation
4/30/10
Add parts to PCB for HV protection
Approved
115338
Waiver
5/1/10
Stress Analysis Part Derating LT1604, OP262 - doc #
116947
MUA
7/15/10
Material Usage Agreement for use of PFTE insulated wire on PWBA
117858
8/27/10
Solder Defects on FPGA Installation
119429
11/30/10
Demoisturization Bake-out Records, S/Ns 1,2,3
In review