1. A high-Precision Timing ASIC for TOF-PET Applications
Pierpaolo Valerio
on behalf of the TT-PET collaboration

2. Outline The TT-PET scanner Front-end architecture System integration
Prototype measurements
Next steps and conclusions
P. Valerio -
13-Sep-17

3. Outline The TT-PET scanner Front-end architecture System integration
Prototype measurements
Next steps and conclusions
P. Valerio -
13-Sep-17

4. The TT-PET collaboration
A 3-yer project to produce a PET Scanner for small animals based on silicon detector technology, insertable in an MRI machine and with 30ps RMS time resolution. The project started in March 2016.
Collaborating institutes:
University of Geneva  Front End Electronics and detector design
University of Bern
Hôpital cantonale de Genève
INFN of Roma Tor Vergata  Front End Electronics and detector design
CERN
Stanford University
P. Valerio -
13-Sep-17

5. Why a Time-of-Flight PET scanner?
Adding Time-of-Flight information to a PET scan can dramatically increase its performance!
It is used to localize the source along the line of flight
It leads to much lower noise, which can be used to increase image quality or decrease radiation dose to the patient
P. Valerio -
13-Sep-17

6. Sensor Layout
Dielectric for signal extraction, capacitive decoupling and low energy electron absorption
Large pixels (1mm2) readout to ensure uniform electric and weighting field
Thin sensor (100µm) to minimize time- walk correction
Monolithic technology: the electronics is embedded in the sensor. No need of wire bonding
High Z converter, thickness optimized with dedicated simulation
Monolithic integration of SiGe Bi-CMOS technology will lead to low cost production of fast, solid state sensors.
P. Valerio -
13-Sep-17 6

7. Scanner Architecture 16 wedge-shaped units, called “cells”
A cell is a stack of ~70 detection layers
Cell efficiency for 511 keV photons: up to 50%.
More than channels on 2112 chips
FEA simulations performed
Cooling Block is currently under revisions for production and tests
Flex design finalized, first prototype in production soon.
Courtesy of L. Paolozzi
P. Valerio -
13-Sep-17 7

8. Pros and cons of this approach
Very high granularity, with access to depth and TOF information for every hit
Faster signals mean ability to have high-precision timing measurements 
The scanner can be designed to be compatible with an MRI scanner, providing combined MRI-PET images
On the other hand...
The mechanics of the scanner are really complex (especially the data flex)
There are a very large number of channels, so the data acquisition scheme is critical
Every channel must be calibrated  very long procedure
P. Valerio -
13-Sep-17

9. Outline The TT-PET scanner Front-end architecture System integration
Prototype measurements
Next steps and conclusions
P. Valerio -
13-Sep-17

10. Analog Front-End
Front-ends sit outside of the active area, at the side of the matrix
PMOS-based resistors
MOS Discriminator
HIT LATCH
To Logic
CAL DAC
Pixel
threshold
P. Valerio -
13-Sep-17

11. Amplifier contribution to time resolution
Detector time resolution depends mostly on the amplifier performance.
𝜎 𝑡 = 𝜎 𝑉 𝑑𝑉 𝑑𝑡 ≅ 𝑡 𝑟𝑖𝑠𝑒 𝑆𝑖𝑔𝑛𝑎𝑙 𝑁𝑜𝑖𝑠𝑒
Pulse time
Threshold
Time
Courtesy of L. Paolozzi
P. Valerio -
13-Sep-17

12. Why SiGe Bi-CMOS – Signal amplification
An intrinsically low series noise  excellent performance for fast pulse integration
High 𝑓 𝑡 at low collector current  fast amplifiers with very low-power consumption
Small size transistors with high 𝛽 at high 𝑓
High gain amplifiers on large capacitance
Performance improvement on small capacitance
Fast growing technology  700 GHz 𝑓 𝑡 transistors under development
P. Valerio -
13-Sep-17

13. Sample Waveform Amplifier output for a 1 fC input signal
Load and feedback PMOS resistive networks were optimized to minimize the time jitter
Large voltage gain reduces the impact of non-idealities in the later stages
The operating point is highly configurable to cope with a range of input capacitances
P. Valerio -
13-Sep-17

14. Main figures of merit
In nominal conditions (from simulations, with 1pF input capacitance):
Gain: 95 mV/fC
ENC: 696.4e-
Power consumption: 135 μW
Peaking time: 1.3 ns
Timing jitter: 82 ps for a 1 fC signal
Average signal in a PET scanner is significantly higher  ~30 ps jitter
Specs can be adjusted by calibrating equivalent resistance values
P. Valerio -
13-Sep-17

15. Discriminating Stage
The discriminator is a 2-stage MOS-based open loop amplifier
Very low power consumption (<20 uW)
An additional hysteresis stage is added to reduce possible bouncing
In order to keep the front-end fast, small input transistor were used, leading to worse mismatch…
… So a 7-bit sub-binary radix current DAC was designed to calibrate the chain
Time-over-Threshold measurement is used to compensate for time- walk errors
TT-PET general meeting
24 Nov 2016

16. Timing measurement chain
HIT LATCH
Balanced Hirearchical OR
HIT LATCH
Hybrid TDC …
Time-of-Flight
+ ToT
HIT LATCH
Position Logic
Position data
P. Valerio -
13-Sep-17

17. Monolithic integration
25 mm
7-11 mm
HV applied on the pixels, inside a Guard Ring.
Amplifiers and comparators as close as possible to the pad.
Time digitization and logic on the short side of the chip
P. Valerio -
13-Sep-17

18. Chip readout
Expected data rate is low enough that an on-chip 2-stage buffering is enough to avoid pile-up
The flex cable layout is critical and very challenging  readout protocol with few lines  chip daisy-chain
Simple programming protocol to configure biasing and pixel calibration
Serial readout at 50 Mbps with an optional triggering system
P. Valerio -
13-Sep-17

19. Outline The TT-PET scanner Front-end architecture System integration
Prototype measurements
Next steps and conclusions
P. Valerio -
13-Sep-17

20. The flex cable Chips are connected through two types of flex cables
A “chip” cable per layer  50 um thick, has to minimize additional pixel capacitance!
A folded “data” cable connecting 5 layers together
Courtesy of D. Forshaw
P. Valerio -
13-Sep-17

21. Inter-chip communication
Data_in
ASIC_1
ASIC_2
ASIC_N
Tower control FPGA
(x16)
Central FPGA
data_out
clock_out …
(trigger) PC
clock_in_sync
P. Valerio -
13-Sep-17

22. Data reconstruction
Data is reconstructed with a filtered back- projection algorithm
The introduction of Timing data significantly reduces reconstruction artifacts
Courtesy of E. Ripiccini
P. Valerio -
13-Sep-17

23. Outline The TT-PET scanner Front-end architecture System integration
Prototype measurements
Next steps and conclusions
P. Valerio -
13-Sep-17

24. First prototypes
A prototype with complete analog front-ends and monolithic structures was submitted at the end of last year
A separate small chip was designed to test the digital logic (and to validate the digital workflow, it’s the first time we use this technology!)
The monolithic pixel was later improved to sustain a higher voltage by avoiding sharp angles as much as possible
P. Valerio -
13-Sep-17

25. Some preliminary results
Tests with Sr-90 source were successful as the distribution peak is clearly visible
Gain is lower than expected, at least partially due to a larger input capacitance
High-threshold
Low-threshold
# hits
ToT [ns]
P. Valerio -
13-Sep-17

26. Some preliminary results
Noise is within the expected simulated value
Tests with high- resistivity substrate show no degradation in performances
P. Valerio -
13-Sep-17

27. Main challenges Keeping the parasitics low is extremely important!
Careful signal routing
Avoid metal filling
The flex cable layout is also critical
Channel uniformity must be ensured as much as possible
Reducing crosstalk is critical…
… although it should be easier in the final chip with shorter routing lines
P. Valerio -
13-Sep-17

28. Other prototypes and ongoing tests
A fully featured prototype was submitted in April
It has a smaller matrix and a simplified readout scheme, but it's otherwise complete
It's useful to test integration issues (power delivery, crosstalk...)
Tests are being set up as we speak
P. Valerio -
13-Sep-17

29. Outline The TT-PET scanner Front-end architecture System integration
Prototype measurements
Next steps and conclusions
P. Valerio -
13-Sep-17

30. Next submissions and design steps
Some more test structures have been submitted to study the monolithic integration and improve isolation structures
Smaller utility blocks are already designed and need to be integrated in the chip (bandgap, rail-to-rail buffers)
After tests on the prototype, a final submission is tentatively scheduled for early next year
P. Valerio -
13-Sep-17

31. Conclusions
A chip for fast TOF measurement for PET applications is being designed using a SiGe BiCMOS technology
SiGe HBT technology was found to be suited to fast-frontends with large input capacitances
First measurements on prototypes show good results which match simulation models
The design is very sensitive to layout effects  extracted simulations and proper routing is critical
Work is ongoing also on other important parts of the system including mechanics, cooling, data acquisition and reconstruction
P. Valerio -
13-Sep-17

32. Thanks for your attention
P. Valerio -
13-Sep-17

33. BACKUP
P. Valerio -
13-Sep-17

34. Minimization of ENC for a fast integrator
Avoid larger analogue bandwidth
𝐸𝑁𝐶 2 ∝ 2 𝑞 𝑒 𝐼 𝐶 + 4𝑘𝑇 𝑅 𝑃 + 𝑖 𝑛𝑎 2 ∙𝜏+ 4𝑘𝑇 𝑅 𝑆 + 𝑒 𝑛𝑎 2 ∙ 𝐶 𝑖𝑛 2 𝜏 +4 𝐴 𝑓 𝐶 𝑖𝑛 2
Dominating term
Excellent performance in terms of series noise for fast shaping are achievable with the BJT technology
𝐸𝑁𝐶 𝑠𝑒𝑟𝑖𝑒𝑠 𝑛𝑜𝑖𝑠𝑒 ∝ 𝐶 𝑖𝑛 2𝑘𝑇 𝑆𝑁𝐼 ℎ 𝑖𝑒 𝛽 + 𝑅 𝑏𝑏
Transistor ENC contribution depends on current gain and base spreading resistance
P. Valerio -
13-Sep-17

35. SiGe technology for very low-noise, fast amplifiers
Amplifier current gain can be expressed as (NPN BJT)
𝛽= 𝑖 𝐶 𝑖 𝐵 = 𝜏 𝑝 𝜏 𝑡
𝜏 𝑝 =hole recombination time in base
𝝉 𝒕 =𝐞𝐥𝐞𝐜𝐭𝐫𝐨𝐧 𝐭𝐫𝐚𝐧𝐬𝐢𝐭 𝐭𝐢𝐦𝐞 (𝐄 𝐭𝐨 𝐂)
Need to minimize electron transit time in the base
Increase gain
Reduce base width
Reducing base doping
Spreading resistance increases!
P. Valerio -
13-Sep-17

36. SiGe technology for very low-noise, fast amplifiers
A possible approach: changing the charge transport mechanisms in the base from diffusion to drift.
SiGe heterojunction bipolar transistor technology.
The technology we chose is
SG13S from IHP:
𝛽=900
𝑓 𝑡 =250 𝐺𝐻𝑧
Equivalent to introducing an electric field in the base.
P. Valerio -
13-Sep-17

37. More details on mechanics
P. Valerio -
13-Sep-17

38. Data Rate
Hit rate for a 50 MBq point source is still < 25KHz per layer
P. Valerio -
13-Sep-17