1. Introduction to VHDL (14 Marks)
CH.3
Introduction to VHDL
(14 Marks)
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2. Introduction to HDL HDL is a hardware description language .
HDL allows write-run-debug cycle for hardware development.
Similar to programming software
Much, much faster than design-implement-debug
Combined with modern Field Programmable Gate Array chips large complex circuits (100000s of gates) can be implemented.

3. Continued---
Similar to programming languages a number of languages have been developed to describe Hardware.
HDL
VHDL Verilog
Both of these HDLs are IEEE standards.
Using HDL, logic circuit is represented in its code which is used for design entry.
This method can be used efficiently designing small as well as large systems.

4. VHDL
VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

5. Funded by the US Department of Defense in the 80's
Continued….
VHDL stands for Very high speed integrated circuit Hardware Description Language
Funded by the US Department of Defense in the 80's
Originally meant for design standardisation, documentation, simulation and ease of maintenance.
Established as IEEE standard IEEE 1076 in An updated standard, IEEE 1164 was adopted in In 1996 IEEE became a VHDL synthesis standard.
Todasimulation and synthesisy VHDL is widely used across the industry for design description,.

6. Histry of VHDL
The development of VHDL was initiated in 1981 by the United States Department of Defence to address the hardware life cycle crisis. The cost of reproducing electronic hardware as technologies became obsolete was reaching crisis point, because the function of the parts was not adequately documented, and the various components making up a system were individually verified using a wide range of different and incompatible simulation languages and tools. The requirement was for a language with a wide range of descriptive capability that would work the same on any simulator and was independent of technology or design methodology.

7. Continued…
1981
Initiated by US DoD to address hardware life-cycle crisis
Development of baseline language by Intermetrics, IBM and TI
1986
All rights transferred to IEEE
1987
Publication of IEEE Standard
Mil Std 454 requires comprehensive VHDL descriptions to be delivered with ASICs
1994
Revised standard (named VHDL )
2000
Revised standard (named VHDL , Edition)

8. Pro’s and con’s of VHDL Pro’s of VHDL 1.Strongly typed language.
Dealing with signed and unsigned numbers is natural, and there’s less chance of making a precision mistake or assigning a 16-bit signal to a 4-bit signal.
2.Ability to define custom types.
A VHDL state machine can be coded naturally using the actual state names (e.g. wait, acknowledge, transmit, receive, etc.), not binary state numbers (e.g. 00, 01, 10, 11).
3.Record types.
Define multiple signals into one type.
Natural coding style for asynchronous resets.
Easily reverse bit order of a word.
Logical statement (like case and if/then) endings are clearly marked.
4.Not Case sensitive

9. Pro’s and Con’s of VHDL 1.Extremely verbose coding.
VHDL modules must be defined by a prototype and declared before they’re used, causing you to change code in at least 3 places if you want to make a change to the interface.
The use of the keyword “downto” in every bit vector definition is tedious.
2.Sensitivity lists.
Missing a single signal in the sensitivity list can cause catastrophic differences between simulation and synthesis.
Each process must have a sensitivity list that may sometimes be very long.
Type conversions.
Signal types that are clearly related (e.g. std_logic and std_logic_vector) cannot be simply used together and must be converted to another type.

10. Entity Architecture Configuration Package Library
VHDL flow elements
Entity
Architecture
Configuration
Package
Library

11. Entity Entity is the description of input and output.
An entity statement declares the input output port.
Each of these entities have their own architecture statement.
Uppermost entity is the top level entity.
Thus all designs contain most important basic block
i.e. entity.
Syntax
Entity name of the entity is
Port(port declarations);
End name of the entity;

12. Architecture Architecture describes the behavior of the entity.
All entities that can be simulated have an architecture
description.
A single entity can have entity can have multiple architecture.
These architecture can have different styles of description of design like behavioral design for one port
and sequential design for other port.
Architecture describes the underlying functionality of entity and contains the statements that models the behavior of entity.
an architecture always related to entity and describes the behavior of entity.

13. Architecture architecture name of entity name is
Continued….
Syntax
Architecture architecture name of entity name is
begin
Statements(relation between input and output);
end architecture name ;

14. Configuration
The configuration does the job of specifying the exact set of entities and architectures used in a particular simulation or synthesis run.
The configuration does the two things
1. A configuration specifies the design entity used in place of each component instance ( i.e. it plugs the chip into chip socket and then socket chip assembly into PCB).
2. Configuration specifies the architecture to be used for each design entity.

15. Continued----- Declaration Syntax
configuration configuration _name of entity_ name is
---- configuration declarations;
for architecture _name
for instsnce_lebel.component_name
use entity library_name.component_name(arch_name);
end for;
end configuration _name ;

16. Package
Package is the collection of commonly used data types and sub programms used in a design.
- set of subprogram to operate on a particular data
type.
- set of declarations for particular model.
- Separate interface from implementation.
- allows declaration of global signals
For example- Clock

17. Declaration Syntax Package identifier is
Continued…
Declaration Syntax
Package identifier is

18. Library Library is a collection of compiled VHDL units.
Library should be declared before each entity of program.
The IEEE created the IEEE VHDL library and std_logic type in standard This was extended by Synopsys; their extensions are freely redistributable.
Parts of the IEEE library can be included in an entity by inserting lines like these before your entity declaration:
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all; No attempt has been made here to be definitive or exhaustive. If you want real answers, read the source code. Links to the code or instructions on how to get it are provided for each section. The source is fairly readable to someone who knows some VHDL.

19. VHDL objects are Constants Variables Signals Files

20. Constants Constant is the object which names specific value.
Name assigned to a specific value of type.
Allow for easy update and redability.
Syntax
Constsnt_name:type_name[:=value];
For Example
Constant PI : Real : = 3.14;
Constant speed : Integer;

21. Variables Variable provide convenient mechanism for local storage.
For example- loop counters, intermediate values.
All variable assignments take place immediately.
No user specified delay is occur.
Declaration syntax
VARIABLE variable _name: type _name[ := value]
For example
VARIABLE opcode : BIT_VECTOR (3 downto 00) :=“ 0000”;
VARIABLE Freq :Integer;

22. Signals Signals used for communication between VHDL components.
Real, Physical signals in system often mapped to VHDL signals.
All VHDL signal signment require either delta cycle or user specified delay before new value is assumed.
Declaration Syntax
signal_ name : type_name[:=value];
For Example
SIGNAL brdy : BIT
Brdy <= ‘ 0’ AFTER 5ns,’1’ AFTER 10ns;

23. File Files provide a way for a VHDL design to
communicate with the host environment
File declarations make a file available for use
to a design
Files can be opened for reading and writing
– In VHDL87, files are into and out of
scope
– In VHDL93 explicit FILE_OPEN() and
FILE_CLOSE() procedures opened and closed when
their associated objects come were added
The package STANDARD defines basic file
I/O routines for VHDL types

24. Data Types
All the objects, the signal, the variable and the constants can be declared using a type specification
to specify the characteristic of the the object.
VHDL contains a wide range of types that can be used to create simple or complex objects.
A type declaration
Type type_name is type_mark

25. Continued….

26. Scalar Type
Scalar type describe objects that can hold, at most, one value at a time.
The type itself contain multiple values, but an object that is declared to be a scalar type can hold , at most , one of the scalar values at any point at that time.
Scalar Types
Integer- Specified integer range
Real Types- Mathematical real numbers
( e.g.0.0 to 35.7)
3. Enumerated Types- Set of user defined values
(e.g. add,mul,div,u- uninitiated,x- unknown,0-logic ‘0’,
1- logic’1’etc)
4. Physical Tyapes- Measurement of some physical quantity
(e.g.length,time,voltage,current etc.)

27. Composite Type A composite type represents collection of values.
Array- Array belongs to a signal type.
An object of array type consist of elements that have same type.
For Example
Signal A : std_logic_vector(7 downto 0);
2. Record Type- An object of a record type is composed od elements of same or different types.

28. Continued…

29. VHDL Operators 1.Logic Opeators-
Logic operators of logic equations and conditional statements.
e.g. AND,OR,NOT,NAND,NOR,XOR,XNOR
2. Relational Operators-
Used in conditional statements.
= equal to
/ = not equal to
< less than
<=less than or equal to
> greater than
>= greater than or equal to

30. Continued…. 3.Adding Operators- + addition - subtraction
& Concatenation Multiplying Operators-
* Multiplication
/ division
mod Modulus
rem remainder

31. Continued…. 5. Miscellanies Operators- ** exponentiation
left operand= integer or floating point
right operand= integer only
abs absolute value
NOT inversion
6. Shift Operator-
sll shift left logical
Srl shift right logical
Sla shift left arithmatic

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Assignment 3 1. State the data types used in VHDL. 2.Write the use and syntax of i)signal ii)Constant 3. State and explain VHDL objects. 4. State the data types used in VHDL. 5.List operators and their operations used in VHDL.
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