1. Lecture 3. Lateches, Flip Flops, and Memory
COSC3330 Computer Architecture
Lecture 3. Lateches, Flip Flops, and Memory
Instructor: Weidong Shi (Larry), PhD
Computer Science Department
University of Houston

2. Sequential Logic Topics
Latches
Flip Flops
Memory
SRAM
DRAM 2 2

3. Extra Credit Problem
Two week to build it
Demonstrate it in class

4. Random Number Generator
Sample Temperature and
Convert into a Single
Digit Output
Use temperature as input for a digit random number generator. Output one digit a time. The designer discovered that the generator produces more 1s then 0s. Can you fix this without changing the generator circuit?

5. Random Number Generator
Competition
Five points extra credit
Only first three correct solutions accepted
Hints
Use sequential circuit
Send your solution (circuit diagram) to me and the TAs
Circuit diagram
Simple explanation how and why it fixes the problem
Temperature
Random Number
Generator
Your
Circuit

6. Sequential Logic
Outputs of sequential logic depend on current inputs and prior input values
Sequential logic might explicitly remember certain previous inputs, or it might distill (encode) the prior inputs into a smaller amount of information called state
The state is a set of bits that contain all the information about the past necessary to explain the future behavior of the circuit
State elements
SR Latch
D Latch
D Flip-flop 6 6

7. SR Latch
One of the simplest sequential circuits is the SR (Set/Reset) latch
It is composed of 2 cross-coupled NOR gates
It has 2 inputs (S, R) and 2 outputs (Q and Q)
When the set input (S) is 1 (and R = 0), Q is set to 1
Set makes the output (Q) to “1”
When the reset input (R) is 1 (and S = 0), Q is reset to 0
Reset makes the output (Q) to “0” 7 7

8. SR Latch Analysis Consider the four possible cases: a) S = 1, R = 0
b) S = 0, R = 1
c) S = 0, R = 0
d) S = 1, R = 1 8 8

9. SR Latch Analysis a) S = 1, R = 0: b) S = 0, R = 1:
then Q = 1 and Q = 0 1 1
then Q = 0 and Q = 1 1 1 9 9

10. SR Latch Analysis c) S = 0, R = 0: d) S = 1, R = 1: We got Memory!
then Q = Qprev and Q = Qprev
We got Memory! 1 1 1 1
then Q = 0 and Q = 0
Invalid state: Q ≠ NOT Q 10 10

11. SR Latch Recap SR latch stores one bit of state
Where is it stored?
SR latch can control the state with S, R inputs
SR latch generates the invalid state when S =1 and R = 1 11 11

12. D Latch D latch solves the problem with SR latch
D latch blocks the invalid state when S =1 and R = 1
D latch separates when and what the state should be changed
D latch has 2 inputs (CLK, D) and 2 outputs (Q, Q)
CLK controls when the output changes
D (data input) controls what the output changes to
Avoids invalid case (Q ≠ NOT Q when both S and R are 1) 12 12

13. D Latch Internal & Operation
D latch operation
When CLK = 1, D passes through to Q (D latch is transparent)
When CLK = 0, Q holds its previous value (D latch is opaque) 1 1 1
Qprev 1 1 1 1 1 13 13

14. D Latch To get a good intuition, think with waveform
D latch has 2 inputs (CLK, D) and 2 outputs (Q, Q)
CLK controls when the output changes
D (data input) controls what the output changes to
To get a good intuition, think with waveform
When CLK = 1, D latch transfers input data (D) to output (Q)
When CLK = 0, D latch maintains its previous value 14 14

15. D Flip-Flop
In digital logic design, it would be very convenient if we can store input data at a certain moment (not during the whole time interval like D latch)
D flip-flop provides that functionality
Q changes only on the rising edge of CLK
When CLK rises from 0 to 1, D passes through to Q
Otherwise, Q holds its previous value
Thus, a flip-flop is called an edge-triggered device because it is activated on the clock edge 15 15

16. D Flip-Flop Internal Circuit
Two back-to-back latches (L1 and L2) controlled by complementary clocks
When CLK = 0
L1 is transparent
L2 is opaque
D passes through to N1
When CLK = 1
L2 is transparent
L1 is opaque
N1 passes through to Q
Thus, on the edge of the clock (when CLK rises from 0 to 1)
D effectively passes through to Q 16 16

17. D Flip-Flop
Note that input data should not be changed around the clock edge for D flip-flop to work correctly 17 17

18. D Flip-Flop
So, D flip-flop has the effect of sampling the current input data at the rising edge of the clock
Note that input data should not be changed around the clock edge for D flip-flop to work correctly 18 18

19. Registers
An N-bit register is a bank of N flip-flops that share a common CLK input, so that all bits of the register are updated at the same time
You can say N-bit flip-flops or N-bit register
Registers are the key building block of sequential circuits 19 19

20. Clock Oscillators 20 20

21. Clock Oscillators in Digital Systems
Virtually all digital systems are essentially operating synchronous to the clock 21 21

22. Clock in Digital Circuit22 22

23. Synchronous Sequential Logic
Output of sequential logic is determined not only by current inputs but also by state stored in registers
When sequential logic is working (updated) at the event (e.g., rising or falling edge) of clock source, we say that the circuit is synchronous to the clock
In other words, if the state is updated at the event of clock source, the circuit is synchronous sequential logic
Virtually all digital systems are essentially synchronous to the clock
Virtually all digital systems are synchronous sequential logic 23 23

24. Memory
Digital systems including computer systems require memories to store data
Registers (made from flip-flops) are kind of memory
Here we study memory arrays that can efficiently store large amounts of data
Such as RAM 24 24

25. Memory Random Access Memory (RAM) Read-Only Memory (ROM)
Static Random Access Memory (SRAM)
Data stored so long as power is applied
6-transistors per cell
Faster
Dynamic Random Access Memory (DRAM)
Require periodic refresh
Smaller (can be implemented with 1 or 3 transistor)
Slower
Can be read and written
Read-Only Memory (ROM) 25 25

26. Robert Dennard A Texan. SMU (BS, MS), Dallas. CMU (PhD) in EE.
Dennard invented one-transistor Dynamic Random Access Memory in 1966 at IBM Research Lab.

27. Examples DDR SDRAM (Double Data Rate Synchronous DRAM)
Widely being used for main memory in computers 27 27

28. Block Diagram of Memory
An M-bit data value can be read or written at each unique N-bit address
N-bit address lines N
Memory
2N words
(M-bit per word)
Example: Byte-addressable 2MB memory
M = 8 (because of byte-addressability)
N = 21 (1 word = 8-bit)
Read/Write
Chip Enable
M-bit Data Output
(for Read/Write) M
RAM/ROM naming convention:
32 X 8, "32 by 8" => 32 8-bit words
1M X 1, "1 meg by 1" => 1M 1-bit words 28 28

29. Memory Organization Example
4 words x 8 bits
Wordline (WL)
2-to-4
Decoder
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit A0 1
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit 2
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit A1 3
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit CS D7 D6 D5 D4 D3 D2 D1 D0
BitLine
Chip Select 29 29

30. How to Address Memory 4 words x 8 bits 2-to-4 Decoder A0=1 1 2 A1=0 3
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
A0=1 1
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit 2
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
A1=0 3
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit CS
Chip Select=1 D7 D6 D5 D4 D3 D2 D1 D0
Access address = 0x1 30 30

31. Static Random Access Memory (SRAM)
6-Transistor SRAM Cell
word
(row select) 1 1
bit
bit
Typically each bit is implemented with 6 transistors (6T)
Read operation
The bitline and its inverse are precharged to Vdd (1)
Then set Wordline (WL) high
Depending on the value stored, either bitline or ~bitline goes low
Write operation
Put the new value on Bitline and its inverse on ~Bitline
Then set the Wordline to high

32. 1-Transistor Memory Cell (DRAM)
Write:
Drive bit line
Select row
Read:
Precharge bit line to Vdd/2
Cell and bit line share charges
Minute voltage changes on the bit line
Sense (fancy sense amp)
Write: restore the value
row select
bit
Read is really a read followed by a restoring write

33. Refresh So after a read, the contents of the DRAM cell are gone
The values are stored in the row buffer
Write them back into the cells for the next read in the future
DRAM cells
Sense Amps
Row Buffer

34. Refresh (2)
Fairly gradually, the DRAM cell will lose its contents even if it’s not accessed
This is why it’s called “dynamic”
Contrast to SRAM which is “static” in that once written, it maintains its value forever (so long as power remains on)
All DRAM rows need to be regularly read and re-written 1
Gate Leakage
If it keeps its value even if power is removed, then it’s “non-volatile” (e.g., flash, HDD, DVDs)

35. Memory Description Capacity of a memory is described as Examples:
# addresses x Word size
Examples:
Memory
# of addr
# of data lines
# of addr lines
# of total bytes
1M x 8
1,048,576 8 20
1 MB
2M x 4
2,097,152 4 21
1K x 4
1024 10
512 B
4M x 32
4,194,304 32 22
16 MB
16K x 64
16,384 64 14
128 KB 35 35

36. Memory with 2 Decoders 8 words x 4 bits A1 1 2 A2 3 CS 1 Chip Select
2-to-4
Row
Decoder
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit A1 1
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit 2
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit A2 3
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit
1-bit CS
Tristate
Buffer
(read) D0 D1 D2 D3 1
Chip Select CS
1-to-2 Column Decoder A0 36 36

37. Read Operation 8 words x 4 bits 2-to-4 Row Decoder 1 A1 2 A2 3 CS1 2 3
8 words x 4 bits A1 A2 D0 D1 D2 D3
A0 = 0 CS
Chip Select
Rd/Wr = 0
2-to-4
Row
Decoder
1-to-2 Column Decoder 37 37

38. Write Operation 8 words x 4 bits 2-to-4 Row Decoder A1 1 2 A2 3 CS1 2 3 A1 A2 D0 D1 D2 D3
A0 = 1 CS
Chip Select
Rd/Wr = 1
2-to-4
Row
Decoder
1-to-2 Column Decoder 38 38

39. Accesses need not be sequential
DRAM Organization
Row Decoder
Memory
Cell Array
0x1FE
Sense Amps
Row Buffer
0x001
0x000
0x002
Column Decoder
Data Bus
Accesses need not be sequential

40. Example: 512Mb 4-bank DRAM (x4)
Row decoder
Row decoder
Row decoder
BA[1:0]
Row decoder
Bank0
16384 x 2048 x 4
A[13:0]
16K
Address
Sense amps
I/O gating
Column decoder
Column decoder
Column decoder
Column decoder
A[10:0]
A DRAM page
= 2kx4 = 1KB
Address Multiplexing
Data out D[3:0]
A x4 DRAM chip

41. Example 41 41