ASIC DESIGN Asim J. Al-Khalili

ASIC DESIGN Asim J. Al-Khalili
1 1

Objectives What technologies are there? Why CMOS? Where are we?
How far we can go What is the worldwide view of microelectronics ? What are the different implementation methods? 2 2

The First Computer 3 Prentice Hall/Rabaey 3

ENIAC - The first electronic computer (1946)
20,000 Vacuum Tubes, it cost $500,000 It could Add, Subtract and store 10-digit decimal numbers in memory It weighted 27 tons, had a size of 80 ft* 8.5 ft* 3 ft, and it required a room of 680 ft2 Consumed 150KW 4 Prentice Hall/Rabaey 4

The First Transistor 1948 5 5

Milestones of IC Development
Beginning of Semiconductor Evolution 1948 Passive and Active Components from Semiconductor Materials 1958 Planar Transistors 1959 Planar Passive and Active Devices Small Scale Integration (SSI)1964 Medium Scale Integration (MSI) 1968 Large Scale Integration(LSI) 1971 Very Large Scale Integration (VLSI) / Ultra Large Scale Integration (ULSI) 1980s System On Chip (SoC) 2000s 6 6

WORLD OF SILICON DOGS EAT DOGS
IC applications are in every aspects of our lives: Computers Toys Consumer electronics Household items Automotive Industrial equipments Military Communications Advertising and Displays Space and Exploration Etc. 7 7

Electronic Circuit Explosion
IC Technology Advances MORE CIRCIUTS ON CHIP LOW MANUFACTURING COSTS MORE COMPLEX MANY NEW PRODUCTS ELECRONIC PRODUCTS NEVER BEFORE POSSIBLE NUMBER OF CIRCUITS TO BE DESIGNED SKY ROCKETED 8 8

Emerging-in-car systems
9 9

The Internet Big Bang 10 10

Internet bandwidth trend
11 11

The Memory Demand 12 12

The Incredible Shrinking Transistor
13 13

Reduction in Feature Size
Reduce transistor and wiring by  14 14

Intel 4004 Micro-Processor 1971
4-bit CPU 2,300 transistors Area of 3 by 4 mm Employed a 10 μm silicon-gate 92,000 instructions/s 740 KHz Clock 16 pin 15 Prentice Hall/Rabaey 15

Intel Pentium (IV) microprocessor 2002
A 'Northwood' core Pentium 4 processor (P4A) Northwood core at 2.2 GHz 2nd cache 512 KB 55 million transistors, 130 nm Technology 16 Prentice Hall/Rabaey 16

MOORE’S LAW 17 17

Intel announces 14 new Ivy Bridge
Processors May. 31, 2012 (8:31 am) By: Matthew Humphries In: Chips, Chips Picks, Geek Pick, News When Intel launched the 22nm Ivy Bridge processors last month, that first batch of quad-core chips was just the beginning. Today, Intel added another 14 processors to the line-up, only this time the chips are mainly dual-core parts catering to a number of different market segments and platforms. . Of the 14 new processors, 6 are classed as desktop chips with power use (TDP) ranging from watts. These consist mainly of new quad-core chips, but one dual-core desktop chip is also listed (i5-3470T). CPU frequency ranges from 2.6GHz to 2.9GHz and maxing out at 3.4GHz using Intel Turbo Boost on the Core i7 chip. .

IBM Creates New Memory Technology 100 Times Faster Than Flash
by Bryan Vore on July 01, 2011 IBM just revealed its new phase-change memory (PCM) tech that could drastically change computing and gaming.   IBM says that PCM is able to write and retrieve data 100 times faster than Flash memory. It also lasts much longer, surviving 10 million write cycles compared to the 3,000cycles of Flash that the average consumer can use. IBM claims that PCM will herald a "paradigm shift“ when it hits the market in 2016.  .

Latest New iTwin tech torrent onto our hard
drives and memory sticks Latest New iTwin tech torrent onto our hard drives and memory sticks Stuck together, the iTwin twins look like a double-ended USB flash memory stick. However, there’s no real storage available in either. Instead, this natty gadget creates a sort of wormhole through the internet, joining together the two computers that the halves of the iTwin are plugged into The Cloud looms above us all, threatening to rain down a tech torrent onto our hard drives and memory sticks, frying their circuits into obsolescence. Thankfully, we’re not quite there yet but the iTwin marks a step in that direction It’s a twin pack of USB sticks that lock into each other, and can transfer files between each other over the web – from thousands of miles apart. .nto

“Driving the Future” with Kingston’s Latest
Memory Technology, Products, and Services Published on June 4, 2012, by Boss Mac - Posted in PR HyperX series memory.. Higher frequencies as well as larger capacities for HyperX series products could be expected in the near future to fulfill the demanding needs of high-end users eMMC: In response to enthusiasm for lighter and thinner ultra-mobile devices (UMDs) like smartphones, tablet PCs, smart TVs, and ultrabooks, Kingston is scheduled to launch a series of comprehensive memory solutions in For high-end smartphones and tablets, eMMC v4.5 products will be released in capacity ranging from 4GB to 64GB before upgrading to eMMC v4.51 with 4GB to 128GB capacity in

TOSHIBA SD Memory Product Name SD-GU064G2 Capacity 64GB Speed Class
UHS-I Mode UHS Speed Class 1 SD Mode Speed Class 10 Maximum read speed 95MB/ sec Maximum write speed 60MB/ sec Interface R104/SDR50/DDR50/HS/DS bus mode, SDCLOCK ≤ 208MHz Signal Voltage UHS-I Mode1.8V, HS/DS Mode 3.3V Power Supply Voltage V Compliant Standard SD Memory Standard Ver.3.01 File Format exFAT FAT32 External Dimensions 32.0mm(L)×24.0mm(W)×2.1mm(T) Weight Approx. Approx. 2g TOSHIBA SD Memory

Toshiba develops, manufactures 19nm generation NAND Flash Memory with world's largest density and smallest die size 128 Gb capacity in a 3-bit-per-cell chip on a 170mm2 die 23 Feb, 2012 TOKYO—Toshiba Corporation (TOKYO: 6502) today announced breakthroughs in NAND flash that secure major advances in chip density and performance. In the 19 nanometer (nm) generation, Toshiba has developed a 3-bit-per-cell 128 gigabit (Gb) chip with the world's smallest[1] die size—170mm2—and fastest write speed[2]—18MB/s of any 3-bit-per-cell device. The chip entered mass production earlier this month .

What's the largest memory stick that you can buy?
It is 256GB. It is a Memory Stick/Flash Drive/USB/Small Little Finger. It is Very Expensive. 128GB$1,499.99 Item# SDCFXP-128G-A91 SanDisk Extreme® Pro™ CompactFlash® 128GB Card with VPG . Jun 19, 2012 SANDISK I .

CHALLENGES MOUNT FOR INTERCONNECT> By Mark LaPedus
There are a plethora of chip-manufacturing challenges for the 20nm> node and beyond. When asked what are the top challenges facing leading-edge chip makers today, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, said it boils down to two major hurdles: lithography and the interconnect. ROUTING CONGESTION RETURNS By Ed Sperling Routing congestion has returned with a vengeance to SoC design, feuled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors. A CALL TO ACTION: HOW 20NM WILL CHANGE IC DESIGN While it brings tremendous power, performance and area advantages, the 20nm process node also comes with new challenges in such areas as lithography, variability, and complexity. Chip Design Chip Designer | July 12, 2012 |

Example of Industrial foundry
GLOBALFOUNDRIES provides advanced semiconductor manufacturing excellence with leading-edge (28nm), mainstream (65nm and 45nm) and mature (0.35um to 0.11um) technology, on both 200mm and 300mm wafers. GLOBALFOUNDRIES has fabrication in Dresden, New York and Singapore, with a network of design and support centers in Silicon Valley, China, Japan, Germany, Singapore, Taiwan and the U.K. LEVERAGING THE PAST By Ann Steffora Mutschler It is easy to forget that not every design today is targeted at 20nm, given the amount of focus put on the bleeding edge of technology. But in fact a large number of designs utilize the stability and reliability of older manufacturing nodes, as well as lower mask costs, by incorporating new design and verification techniques,

3D design 3D design opens up architectural possibilities for engineering teams to realize much better performance and far less power consumption The greatest power savings in 3D designs are achieved at the architectural level, and that may mean jumping in at the deep end. Hot topic: Thermal integrity's effect on 3D-IC design and analysis.

Gigabyte X11 carbon-fiber laptop is world’s lightest
May. 31, 2012 (7:34 am) By: Matthew Humphries Gigabyte has unveiled a new 11.6-inch laptop called the X11 today, and the Taiwanese company can make two bold claims about the new machine. The X11 is the first all-carbon-fiberlaptop ever released, but more impressively, the X11 is also the lightest laptop in the world. The 11.6-inch MacBook Air weighs a mere 1,080 grams, but the X11 has it beat. It comes in 105 grams lighter at just 975 grams.

What Comes After FinFETs?
What Comes After FinFETs? By Mark LaPedus  The semiconductor industry is currently making a major transition from conventional planar transistors to finFETs starting at 22nm. The question is what’s next? In the lab, IBM, Intel and others have demonstrated the ability to scale finFETs down to 5nm or so. If or when finFETs runs out of steam, there are no less than 18 different next generation candidates that could one day replace today’s CMOS-based finFET transistors. But even the large companies with deep pockets don’t have the time or resources to work on all technologies. “We can’t pick 18,” said Mike Mayberry, vice president and director of components research in the Technology and Manufacturing Group at Intel Corp. “We will develop only a few of them.” Mayberry said the eventual winners and losers in the next-generation transistor race will be determined by cost, manufacturability and functionality. “The best device is the one you can manufacture,” he said. In fact, the IC industry is already weeding out the candidates. In 2005, the Semiconductor Research Corp. (SRC), a chip R&D consortium , launched the Nanoelectronics Research Initiative (NRI), a group that is researching futuristic devices capable of replacing the CMOS transistor in the 2020 timeframe. NRI member companies include GlobalFoundries, IBM, Intel, Micron and TI.

The 4 biggest FPGA producers are :
.June 2011 The 4 biggest FPGA producers are : Xilinx 2.4 Billion$ in % of US mrket Altera 40% 1. Billion955 Quick Logic 1% 26 Million$ MicriSemi 4% 207 Million $ Lattice Semi 6% Million Xilinx and Altera have 89% of the Market With the top two FPGA companies taking up 89% of the FPGA market, you can be forgiven for thinking there was no one else out there. Xilinx and Altera have done a good job of defending the duopoly but a few companies are gradually winning market share by targeting specific applications

FPGA Comparison Table Features Artix-7 Kintex-7 Virtex-7 Spartan-6
Logic Cells 352,000 480,000 2,000,000 150,000 760,000 BlockRAM 19Mb 34Mb 68Mb 4.8Mb 38Mb DSP Slices 1,040 1,920 3,600 180 2,016 DSP Performance (symmetric FIR) 1,248GMACS 2,845GMACS 5,335GMACS 140GMACS 2,419GMACS Transceiver Count 16 32 96 8 72 Transceiver Speed 6.6Gb/s 12.5Gb/s 28.05Gb/s 3.2Gb/s 11.18Gb/s Total Transceiver Bandwidth (full duplex) 211Gb/s 800Gb/s 2,784Gb/s 50Gb/s 536Gb/s Memory Interface (DDR3) 1,066Mb/s 1,866Mb/s 800Mb/s PCI Express® Interface Gen2x4 Gen2x8 Gen3x8 Gen1x1 Agile Mixed Signal (AMS)/XADC Yes Configuration AES I/O Pins 600 500 1,200 576 I/O Voltage 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.5V, 1.8V, 2.5V EasyPath Cost Reduction Solution -

Sensordrone lets you measure everything with your smartphone
Jun. 11, 2012 (5:04 pm) By: Russell Holly In: Mobile, News Smartphones also make the ultimate multitool. I find myself increasing grabbing my phone when I am in the middle of a project — it becomes my flashlight in the dark, my level when hanging a picture, a calculator, and a notepad. But as great as out phones are, they are still limited by the sensors [...]

The Future for Feature Size
33 33

The Future of Junction Depth
34 34

The Future of Gate Delays
35 35

The Future of Number of PINS
36 36

Future of gate and interconnect delays
37 37

Power density Evolution
Watts/cm2 Feature size (µm) 38 38

Power Consumption 39 39

The Future for Supply Voltage
40 40

Optical Communications
41 41

A day made of Glass

Gigabyte pushes the Ivy Bridge Core i7 3770K to 7.032GHz
Geek.com - Chips

A Typical CHIP 44 44

Design Abstraction Levels
SYSTEM MODULE + GATE CIRCUIT DEVICE G D S n+ n+ 45 Prentice Hall/Rabaey 45

CMOS System Design Top-down Design: Bottom-up design:
Design starts at System Specification and works its way to bottom, ie. circuit level Bottom-up design: Design starts at the basic circuits and works upwards towards system level structure 46 46

THE DESIGN FLOW 47 47

Verify at every step Structural Functional Logic Circuit Device Layout
CPU MEMORY Functional Structural Logic Circuit Device Layout 48

Design Strategies Hierarchy
A repeated process of dividing large modules into smaller sub-modules until the complexity of sub-modules are at an appropriately comprehensible level of detail. Parallel hierarchy is implemented in all domains.

A Structured Design Regularity Modularity Locality
Divide the hierarchy in to similar building blocks whenever possible. Some programmability could be added to achieve regularity. Modularity Well defined behavioural, structural and physical interface. Helps: divide tasks into well defined modules, design integration, aids in team design. Locality Internals of the modules are unimportant to any exterior interface.

IC Design Methodology Requirement specification
most important function which impacts the ultimate success of an IC relates to how firm and clear the device specifications are. Device specification may be updated throughout the design cycle. Main items in the specifications are: functional intent: brief description of the device, the technology and the task it performs. Packaging specification device port number package type, dimension, material

Functional Description
high-level block diagram: all major blocks including intra block connections and connections to pin-outs indicating direction and signal flow. Intra block signal function: description of how blocks interact with each other supported with timing diagram where necessary. Internal block description of internal operation of each block. Where necessary, the following to be included: timing diagram, state diagram, truth table.

Specifications I/O specifications D.C. specifications pin-out diagram
I/O functional description loading ESD requirements latch-up protection D.C. specifications absolute maximum ratings for: supply voltage, pin voltages main parameters: VIL and VIH for each input, VOL and VOH for each output, input loading, output drive, leakage current for tri-state operation, quiescent current, power-down current (if applicable)

Specification, continued
AC specifications inputs: set-up and hold times, rise and fall times outputs: propagation delays, rise and fall times, relative timing critical thinking Environmental requirements operating temperature, storage temperature, humidity condition (if applicable) Testing

Device Specification Functional intent: briefly describe the device, the technology, and the circuits it will replace as well as the task it will perform. Design concept pin-out diagram: describe the device using a block diagram of the external view of the chip - basically, a box with all the I/O pins labelled and numbered I/O description: use a chart to define the I/O signals shown in the pin-out diagram

Example:

Functional Specification
internal block diagram: draw blocks for major functions, show all connections including: connection to all pin-outs, connections between blocks, and direction of signal flow Inter-block signal function: describe how the blocks interact with each other and support this with timing diagrams where necessary internal block description: describe the internal operation of each block. When necessary, include: timing diagrams, state diagrams, and truth table

Operating characteristics Absolute maximum stress ratings. Example:

Requirements Operating power and environmental requirement:
power supply voltage operating supply current (specify conditions, e.g., power up, power down, frequency, output conditions) storage temperature operating temperature humidity conditions (if applicable)

Input characteristics
Input characteristics. Example chart: (V reference is VSS = 0, temperature range is 0oC to 70oC)

A Structured Design Regularity Modularity Locality
Divide the hierarchy in to similar building blocks whenever possible. Some programmability could be added to achieve regularity. Modularity Well defined behavioural, structural and physical interface. Helps: divide tasks into well defined modules, design integration, aids in team design. Locality Internals of the modules are unimportant to any exterior interface.

Aim of CMOS system Design
High Density Fast Switching Time Low Power Dissipation Testable Design Regular and Modular Design 62 62

System Performance This is related to several factors including:
Algorithm design Design strategy Circuit implementation Floor plan Interconnect strategy Input/Output drives and coupling Clock distribution Interfacing 63 63

Standard Devices General purpose use --not optimized to a specific application * Fixed or programmable * Available in various complexities: SSI, MSI, LSI, VLSI, and ULSI * Function: standard logic, MPU, memories, DSP, analog functions * Available in a variety of packages * Technology: bipolar, nMOS, CMOS, BiCMOS, GaAs * Occupy larger areas and consume more power compared to other types of ICs 64 64

Full Custom HAND CRAFTED DESIGNG * STRUCTURED DESIGN
HIERARCHIAL: TOP DOWN DESIGN, BOTTM UP DESIGN * EXTENSIVE VERIFICATION * MIXED DIGITAL AND ANALOG * TIME CONSUMING AND EXPENSIVE * REQUIRES EXTENSIVE DESIGN EXPERIENCE * COST EFFECTIVE FOR LARGE PRODUCTION VOLUMES 65 65

GATE ARRAY CONSISTS OF TRANSISTOR ARRAYS
* CUSTOMER DEFINES INTERCONNECTION BETWEEN TRANSISTORS * VENDOR PROVIDES INTERCONNECTION TOPOLOGIES TO FORM LOGIC FUNCTIONS * 1 TO 6 LEVELS OF METALIZATION * AVAILABLE IN DIFFERENT TECHNOLOGIES * TO 5,000,000 GATE LOGIC COMLEXITIES. * 2 TO 4 WEEKS DESIGN LEAD TIME 66 66

STANDARD CELLS *PREDESIGNED AND PRECHARACTERIZED CELLS
* AVAILABLE IN VARIOUS CELL COMPLEXITIES: MACROCELLS --VARIABLE HEIGHTS MICROCELLS--STANDARD HEIGHTS * DESIGN PHILOSOPHY SIMILAR TO OFF THE SHELF COMPONENTS * MORE EFFICIENT SILICON UTILIZTION COMPARED * MEDIUM DESIGN TIME * LOWER COST * COST EFFECTIVE FOR LARGE PRODUCTION VOLUMES* 67 67

CELL TOPOLOGY STANDARD CELLS ARE AVAILABLE AS FIXED HEIGHT OR VARIABLE HEIGHT. *FIXED HEIGHT CELLS: --MAJORITY OF CELLS ARE IMPLEMENTED USING -- FIXED HEIGHT, BUT VARIABLE WIDTH LAYOUT -- CELLS ARE STACKED IN ROWS * VARIABLE HEIGHT CELLS : --FOR MORE COMPLEX FUNCTIONS SUCH AS MEMORY, ALU, MICROPROCESSOR * COST EFFECTIVE FOR LARGE PRODUCTION VOLUMES 68 68

AIMs What the customers want: What the Employer wants
High Quality Low Cost Small Size/Weight What the Employer wants Design the: Best Cheapest In shortest time Follow the Spec or better. What you (chip designer) should do: Design a chip with: High speed Small area Low power Testable and reliable Delivered in a short time 69

Web http://www.ece.concordia.ca/~asim
Instructor Name: Asim Al-Khalili Office: EV5.126 Tel: ext.3119, FAX Web Time: Mondays-Wednesdays 16:15-17:30 Class Room: MB Office hours: Mondays 2:00- 3:00 Course Outline Reference Materials Assignments Lectures Information Announcements Tools Project Useful Files Important Dates: Midterm Exam: ,Monday 21st Oct,2013 Final Exam: Exam: To be announced Project Delivery: Monday . Monday 19h Dec. 2:00 PM. To be handed to me in my room or the Secretary at front desk. Web Information 70

The following topics will be covered:
Week_1 Introduction to ASIC design and review materials. Week_2 MOS transistor characteristics. Week_3 DC analysis of CMOS logic family. Week_4 RC time models, interconnect models. Week_5 Transient analysis, propagation delay models. Week_6 CMOS gates and Static logic families. Week_7 Memory elements. Clocking strategies. Week_8 CMOS process and layout generation. Week_9 Layout techniques. Week_10 I/O drivers and circuit protection. Week_11 Circuit Optimization and secondary effects. Week_12 Dynamic logic families. Week_13 Design for Testability, Packaging, PLD, Synthesis issues. Laboratory: H915. The lab is conducted as an open concept, with no schedule. Information on lab usage will be provided in class. Grading: 5% Assignment Midterm 15% % project, 60% Final Exam Text: “CMOS Digital Integrated Circuits, Analysis and Design” (Recommended ) By Sung-Mo Kang and Yusuf Leblebici,3rd Edition, Published by McGraw-Hill “Principles of CMOS VLSI Design” By N. H. Weste & K. Eshraghian 2nd Edition, Published by Addison Wesley “ Application Specific Integrated Circuits”, By M. J. S. Smith,,Addison Wesley 71

Combinational and sequential Logic Circuits
Device Physics Device Electronics Transistor Circuits Covered in COEN 451 Combinational and sequential Logic Circuits Regular and irregular Subsystems System related issues including reliability, DFT 72

Course Project The course requires: design, Design Verification
Layout, Layout Verification, DRC Post Layout Simulation, Characterization IN/OUT placement An example of students projects follows: 73

Ji, Haiying Zhang, Haiqing
A 4-Bit Synchronous Up/Down Counter -- Project of ASIC Design -- Instructor: Dr. A.J.AL-Khalili Submitted by Ji, Haiying Zhang, Haiqing Submitted Date: 29 April, 2002 74 74

Overview Logic Design Specification: exhibiting our logic design of every unit: half adder/subtracter, one-bit counter, 4-bit counter. Logic circuit simulation result is presented. The stage mainly worked on the Synopsys development platform within UNIX. Circuit Design Specification: fully covering the most of our work about every CMOS logic circuit unit: NAND and NOR gates, D flip-flop etc. All parameters of circuits are decided. And there are some the circuit plots and waveforms generated by Cadence development tools that test and verify every part of our CMOS circuit design. Layout and Simulation: With Cadence layout tool, we drew the layouts of all circuit units according to the design parameter from the last design stage. Perform DRC. Extract the design and simulate it again and characterize the two gates. To perform DRC on the final design, extract it and simulate it again to obtain the performance measures. The waveforms related the design are shown and analyzed. Packaging: The procedure to place and rout the complete chip including all I/O drivers and PADs is presented. Analyzing and Summary: The test results were analyzed carefully and helped us got appropriate conclusion. Give a complete specification for the circuit. It is summary of our work. It manifests our great gain of designing and developing work experience and important realization from this course. Appendix: this is needful supplement showing our coding work in logic design stage and perfect layout picture drawn with Cadence layout tools. 75

78 In1 S udcontrol In2 Bor/Car D Q CLR CLK Data i Control Input

Circuit Design D flip-flop circuit design 81

Parameters for positive-edge-triggered D flip-flop.
minimum Typical Maximum Unit fMAX maximum clock frequency ------ 1670 MHz tPLH propagation delay time, low-to-high output from clear Ns tPHL propagation delay time, high-to-low output from clear 0.1 tPLH propagation delay time, low-to-high output from clock 0.18 0.2 0.22 tPHL propagation delay time, high-to-low output from clock 0.17 Width of clock or clear pulse, tw 0.3 Setup time, tsu Data hold time, th 0.08 Supply voltage, VDD 3.3 Volt 82

Timing waveforms of DFF
83

Half Adder/Subtracter Circuit
84

Half Adder/Subtracter Circuit waveforms
85

Half Adder/Subtracter Timing parameters
Typical Unit tPLH propagation delay time, low-to-high sout from data input 0.34 ns tPHL propagation delay time, high-to-low sout from data input 0.38 tPLH propagation delay time, low-to-high sout from udctrl 0.24 tPHL propagation delay time, high-to-low sout from udctrl 0.26 Sout rise-time, tr 0.1 Sout fall-time, tf Borcar fall-time, tr Borcar fall-time, tf Supply voltage, VDD 3.3 Volt 86

4-bit synchronous up/down counter design
4-bit synchronous up down counter implementation 87

waves feature for the 4-bit synchronous up down counter
88

Timing parameters for the 4-bit synchronous up down counter
Typical Unit tPLH propagation delay time, low-to-high sout from clock input 0.34 ns tPHL propagation delay time, high-to-low sout from clock input 0.43 tPLH propagation delay time, low-to-high sout from udctrl 0.68 tPHL propagation delay time, high-to-low sout from udctrl 0.60 Sout rise-time, tr 0.38 Sout fall-time, tf 0.36 Borcar fall-time, tr 0.1 Borcar fall-time, tf Supply voltage, VDD 3.3 Volt 89

Layout and Simulation NAND Gate Layout 90

simulation waveforms of NAND gate
91

Simulation characteristics of the 2-input NAND gate in complementary CMOS.
DC characteristics Active area Total area Static current VOH VOL VIH VIL NML NMH 18.76 um2 132.5 um2 3.3 volts 0 volt 1.42 volts 0.87 volts 1.88 volts AC characteristics tPLH min tPHL tP max tr tf Average power Peak Power 0.15 ns 0.03 ns 0.09 ns 0.18 ns 0.05 ns 0.115 ns 0.14 ns 0.176 ns 0.43 mw 0.5 mw 92

NOR Gate Layout 93

Waveform of the 2-input NOR gate in complementary CMOS.
94

Simulation characteristics of the 2-input NOR gate in complementary CMOS
DC characteristics Active area Total area Static current VOH VOL VIH VIL NML NMH 24.87 um2 um2 3.3 volts 0 volts 1.57 volts 0.95 volts 1.73 volts AC characteristics tPLH min tPHL tP max tr tf Average power Peak Power 0.18 ns 0.05 ns 0.115 ns 0.2 ns 0.07 ns 0.135 ns 0.2 ns 0.15 ns 0.24 ns 0.16 ns 0.45 mw 0.6 mw 95

Transmission Gate Layout
96

Inverter Gate Layout 97

DFF Layout 98

Half Adder/Substrater Layout
99

4-bit synchronous up/down counter layout
100

Simulation waveforms of 4-bit synchronous up/down counter layout
101

Simulation characteristics of 4-bit synchronous up/down counter layout
DC characteristics Active area Total area Static current VOH VOL VIH VIL NML NMH Input leakage current 2685 um2 16000 um2 3.3 volts volt 1.5 volts 0.9 volts 1.8 volts 2 uA Prerequisite for switching function Maximum frequency fma Minimum CLK width CLR width Set up time tsu uctrl to CLK Set up time tsu CLR to CLK Hold time th uctrl to CLK Hold time th CLR to CLK 280 MHz 3.5 ns 1.6 0.8 0.3 0.15 Switching characteristics tPLH tPHL tPudctrl to output tPLH tPHL tPCLK to output tPLH tPHL tP CLR to output 0.7 ns 0.665ns 0.72 ns 0.693 ns 0.8 ns 102

Package I/O structure of the 4-bit synchronous up down counter.
Ø Input pads In our chip we have three input pads: CLK, CLR, and udctrl. We use the pads of PADINC in hcells library, then make the connection with the correspondent input in the counter circuit using metal1dg layer. Ø Output pads In our chip we have five output pads: output<0>, output<1>, output<2>, output<3>, and brwcry (borrow carry). The first four outputs are the counting results, and the brwcry output pad provides a function of forming cascaded counter using this counter. Notes: -udctrl-- up/down control signal; CLK-- clock signal; CLR-- clear signal -CLR is a high- active signal, so there is no tPLH from CLR to output. 103

Pad Layout of the 4-bit synchronous up down counter.
104

Analyzing & Summary From the three development stages, logic design, circuit design and layout simulation, we are able to acquire the conclusion easily. The logic design simulation is the ideal wave that we want to get. The circuit design simulation verifies our logic design correct and in this stage it also help us decide the appropriate parameters. The layout is based on our circuit design parameter. Its simulation result proves to our design work successful. What should be advanced is the fact that there is some discrepancy between the two results from circuit design simulation and layout simulation. As the shown in the Figure 5-5 and Figure 4-10, all the time performance parameters from layout simulation are higher those from circuit design simulation. Actually it is just right result that we have predicted. The layout is closer to real product. However, the circuit design mainly simulates the ideal model; some effect resulting from whole circuit can not be calculated accurately. In short, our work is proved to be significant. Through the project we have learned more system development knowledge and strengthened the ASIC design skills. The achievement from that also manifests our team is successful and cooperative. In addition, we understand the challenge projects in the future work and how to face and solve them. Again, we express our appreciation for our tutor Dr. A.J.AL-Khalili. 105

Verify at every step Structural Functional Logic Circuit Device Layout
CPU MEMORY Functional Structural Logic Circuit Device Layout 106

Fabrication Process Crystal Growth Doping Deposition Patterning
Lithography Oxidation Ion Implementation 107

Fabrication- CMOS Process
Starting Material Preparation 1. Produce Metallurgical Grade Silicon (MGS) SiO2 (sand) + C in Arc Furnace Si- liquid 98% pure 2. Produce Electronic Grade Silicon (EGS) HCl + Si (MGS) Successive purification by distillation Chemical Vapor Deposition (CVD) 108

Fabrication: Crystal Growth
Czochralski Method Basic idea: dip seed crystal into liquid pool Slowly pull out at a rate of 0.5mm/min controlled amount of impurities added to melt Speed of rotation and pulling rate determine diameter of the ingot Ingot- 1to 2 meter long Diameter: 4”, 6”, 8” 109

Fabrication: Wafering
Finish ingot to precise diameter Mill “ flats” Cut wafers by diamond saw: Typical thickness 0.5mm Polish to give optically flat surface 110

Fabrication: Oxidation
Silicon Dioxide has several uses: - mask against implant or diffusion - device isolation - gate oxide - isolation between layers SiO2 could be thermally generated or through CVD Oxidation consumes silicon Wet or dry oxidation Quartz Tube Wafers Quartz Carrier Resistance Heater O 2 or Water Vapor Pump 111

Fabrication: Diffusion
Simultaneous creation of p-n junction over the entire surface of wafer Doesn’t offer precise control Good for heavy doping, deep junctions Two steps: Pre-deposition Dopant mixed with inert gas introduced in to a furnace at 1000 oC. Atoms diffuse in a thin layer of Si surface Drive-in Wafers heated without dopant Temp: 1000 wafers Dopant Gas Resistance Heater 112

Fabrication: Ion Implantation
Precise control of dopant Good for shallow junctions and threshold adjust Dopant gas ionized and accelerated Ions strike silicon surface at high speed Depth of lodging is determined by accelerating field 113

Fabrication: Deposition
Used to form thin film of Polysilicon, Silicon dioxide, Silicon Nitride, Al. Applications: Polysilicon, interlayer oxide, LOCOS, metal. Common technique: Low Pressure Chemical Vapor Deposition (CVD). SiO2 and Polysilicon deposition at 300 to 1000 oC. Aluminum deposition at lower temperature- different technique Torr Loader Pump Reactant 114

Fabrication: Metallization
Standard material is Aluminum Low contact resistance to p-type and n-type When deposited on SiO2, Al2O3 is formed: good adhesive All wafer covered with Al Deposition techniques: Vacuum Evaporation Electron Beam Evaporation RF Sputtering Other materials used in conjunction with or replacement to Al 115

Fabrication: Etching Wet Etching
Etchants: hydrofluoric acid (HF), mixture of nitric acid and HF Good selectivity Problem: - under cut - acid waste disposal Dry Etching Physical bombardment with atoms or ions good for small geometries. Various types exists such as: Planar Plasma Etching Reactive Ion Etching Plasma Reactive species RF 116

Fabrication: Lithography
Mask making Most critical part of lithography is conversion from layout to master mask Masking plate has opaque geometrical shapes corresponding to the area on the wafer surface where certain photochemical reactions have to be prevented or taken place. Masks uses photographic emulsion or hard surface Two types: dark field or clear field Maskmaking: optical or e-beam 117

Lithography: Mask making
Optical Mask Technique 1. Prepare Reticle Use projection like system: -Precise movable stage -Aperture of precisely rectangular size and angular orientation -Computer controlled UV light source directed to photographic plate After flashing, plate is developed yielding reticle 118

Step & Repeat Printing Printing 119

Electron Beam Technique Main problem with optical technique: light diffraction System resembles a scanning electron microscope + beam blanking and computer controlled deflection 120

Patterning/ Printing Process of transferring mask features to surface of the silicon wafer. Optical or Electron-beam Photo-resist material (negative or positive):synthetic rubber or polymer upon exposure to light becomes insoluble ( negative ) or volatile (positive) Developer: typically organic solvant-e.g. Xylen A common step in many processes is the creation and selective removal of Silicon Dioxide 121

Patterning: Pwell mask
122

Patterning/ Printing SiO2 substrate 123

Fabrication Steps Post bake Etch Strip resist mask Pre-bake Apply PR
Inspect, measure Post bake Etch Develop, rinse, dry Strip resist mask Printer align expose Deposit or grow layer Pre-bake Apply PR 124

Fabrication Steps 125

Fabrication Steps: P-well Process
VDD Diffusion P+ P+ Vin Vo P well n n+ p+ p p+ p+ n+ n+ Substrate n-type P well 126

Fabrication Steps: P-well Process
VDD Diffusion P+ P+ Vin Vo P well n n+ p+ p p+ p+ n+ n+ Substrate n-type P well 127

Fabrication Steps n+ n+ p+ p+ P well n+ Substrate n-type n+ p+ p+
128

Fabrication Steps Oxidation Substrate n-type Patterning of P-well mask
oxide Substrate n-type Patterning of P-well mask Substrate n-type 129

Fabrication Steps Diffusion: p dopant, Removal of Oxide Si3N4
P-well Si3N4 Deposit Silicon Nitride P-well 130

Fabrication Steps Patterning: Diffusion (active) mask substrate
P-well substrate Oxidation FOX FOX FOX substrate 131

Fabrication Process Crystal Growth Doping / Diffusion Deposition
Patterning Lithography Oxidation Ion Implementation 132 132

Fabrication- CMOS Process
Starting Material Preparation 1. Produce Metallurgical Grade Silicon (MGS) SiO2 (sand) + C in Arc Furnace Si- liquid 98% pure 2. Produce Electronic Grade Silicon (EGS) HCl + Si (MGS) Successive purification by distillation Chemical Vapor Deposition (CVD) 133 133

Fabrication: Crystal Growth
Czochralski Method Basic idea: dip seed crystal into liquid pool Slowly pull out at a rate of 0.5mm/min controlled amount of impurities added to melt Speed of rotation and pulling rate determine diameter of the ingot Ingot- 1to 2 meter long Diameter: 4”, 6”, 8” 134 134

Fabrication: Wafering
Finish ingot to precise diameter Mill “ flats” Cut wafers by diamond saw: Typical thickness 0.5mm Polish to give optically flat surface 135 135

Fabrication: Oxidation
Silicon Dioxide has several uses: - mask against implant or diffusion - device isolation - gate oxide isolation between layers SiO2 could be thermally generated or through CVD Oxidation consumes silicon Wet or dry oxidation Quartz Tube Wafers Quartz Carrier Resistance Heater O 2 or Water Vapor Pump 136 136

Fabrication: Diffusion
Simultaneous creation of p-n junction over the entire surface of wafer Doesn’t offer precise control Good for heavy doping, deep junctions Two steps: Pre-deposition Dopant mixed with inert gas introduced in to a furnace at 1000 oC. Atoms diffuse in a thin layer of Si surface Drive-in Wafers heated without dopant Temp: 1000 wafers Dopant Gas Resistance Heater 137 137

Fabrication: Ion Implantation
Precise control of dopant Good for shallow junctions and threshold adjust Dopant gas ionized and accelerated Ions strike silicon surface at high speed Depth of lodging is determined by accelerating field 138 138

Fabrication: Deposition
Used to form thin film of Polysilicon, Silicon dioxide, Silicon Nitride, Al. Applications: Polysilicon, interlayer oxide, LOCOS, metal. Common technique: Low Pressure Chemical Vapor Deposition (CVD). SiO2 and Polysilicon deposition at 300 to 1000 oC. Aluminum deposition at lower temperature- different technique Torr Loader Pump Reactant 139 139

Fabrication: Metallization
Standard material is Aluminum Low contact resistance to p-type and n-type When deposited on SiO2, Al2O3 is formed: good adhesive All wafer covered with Al Deposition techniques: Vacuum Evaporation Electron Beam Evaporation RF Sputtering Other materials used in conjunction with or replacement to Al In today’s technology are cupper and its alloys. 140 140

Fabrication: Etching Wet Etching
Etchants: hydrofluoric acid (HF), mixture of nitric acid and HF Good selectivity Problem: - under cut - acid waste disposal Dry Etching Physical bombardment with atoms or ions good for small geometries. Various types exists such as: Planar Plasma Etching Reactive Ion Etching Plasma Reactive species RF 141 141

Mask making Most critical part of lithography is conversion from layout to master mask Masking plate has opaque geometrical shapes corresponding to the area on the wafer surface where certain photochemical reactions have to be prevented or taken place. Masks uses photographic emulsion or hard surface Two types: dark field or clear field Maskmaking: optical or e-beam 142 142

Optical Mask Technique 1. Prepare Reticle Use projection like system: -Precise movable stage -Aperture of precisely rectangular size and angular orientation -Computer controlled UV light source directed to photographic plate After flashing, plate is developed yielding reticle 143 143

Step & Repeat Printing Printing 144 144

Electron Beam Technique Main problem with optical technique: light diffraction System resembles a scanning electron microscope + beam blanking and computer controlled deflection 145 145

Patterning/ Printing Process of transferring mask features to surface of the silicon wafer. Optical or Electron-beam Photo-resist material (negative or positive):synthetic rubber or polymer upon exposure to light becomes insoluble ( negative ) or volatile (positive) Developer: typically organic solvant- e.g. Xylen A common step in many processes is the creation and selective removal of Silicon Dioxide 146 146

Patterning: Pwell mask
147 147

Patterning/ Printing SiO2 substrate 148 148

Fabrication Steps Inspect, measure Post bake Etch Develop, rinse, dry
Strip resist Printer align expose mask Deposit or grow layer Pre-bake Apply PR 149 149

Fabrication Steps 150 150

3D Perspective 151 151

The Physical Structure (NMOS)
Gate oxide Polysilicon Gate Al Al SiO2 SiO2 SiO2 S D Field Oxide Field Oxide n+ channel n+ L P Substrate contact Metal (G) L (S) n+ n+ (D) W Poly 152 152

153 153

The Physical Structure (NMOS)
Gate oxide Polysilicon Gate Al Al SiO2 SiO2 SiO2 S D Field Oxide Field Oxide n+ channel n+ L P Substrate contact Metal (G) L (S) n+ n+ (D) W Poly 154 154

3D Perspective 155 155

ASIC DESIGN Asim J. Al-Khalili

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ASIC DESIGN Asim J. Al-Khalili

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