1. CHAPTER 13 Fabrication of Microelectronic and Micromechanical Devices

2. Pentium Processor
FIGURE (a) A completed eight-inch wafer with completed dice. (b) A single chip in a dual in-line package (DIP) with cover removed. (c) A printed circuit board. Source: Courtesy Intel Corporation.

3. Fabrication of Semiconductor
FIGURE Cross-sectional views of the fabrication of a metal oxide semiconductor. Source: R. C. Jaeger.

4. Fabrication Sequence for Integrated Circuits
FIGURE General fabrication sequence for integrated circuits.

5. Crystallographic Structure of Silicon
FIGURE Crystallographic structure and Miller indices for silicon. (a) Construction of a diamond-type lattice from interpenetrating face-centered cubic cells (one of eight penetrating cells shown). (b) The diamond-type lattice of silicon. The interior atoms have been shaded darker than the surface atoms. (c) The Miller indices for a cubic lattice.

6. Single-Crystal Wafers of Silicon
FIGURE Identification of single-crystal wafers of silicon.

7. CVD Reactors
FIGURE Schematic diagrams of (a) a continuous, atmospheric-pressure CVD reactor and (b) a low-pressure CVD reactor. Source: S.M. Sze. (c) Apparatus for ion implantation. Source: J.A. Schey.

8. Growth of Silicon Dioxide
FIGURE Growth of silicon dioxide, showing consumption of silicon. Source: S.M. Sze.

9. Lithography Techniques
TABLE General characteristics of lithography techniques.

10. Pattern Transfer by Lithography
FIGURE Pattern transfer by lithography. Note that the mask in Step 3 can be either a positive or a negative image of the pattern. Source: After W. C. Till and J. T. Luxon.

11. Etching Directionality
FIGURE Etching directionality. (a) Isotropic etching: Etch proceeds vertically and horizontally at approximately the same rate, with significant mask undercut. (b) Orientation-dependant etching (ODE): Etch proceeds vertically, terminating on {111} crystal planes with little mask undercut. (c) Vertical etching: etch proceeds vertically with little mask undercut. Source: Courtesy of K. R. Williams, Agilent Laboratories.

12. Etch Rates of Silicon
FIGURE Etch rates of silicon in different crystallographic orientations, using ethylene-diamine/pyrocatechol-in-water as the solution. Source: After H. Seidel et al., J. Electrochemical Society, 1990, pp

13. Membrane and Orifice Formation
FIGURE Application of a boron etch stop and back etching to form a membrane and orifice. Source: After Il Brodie and J. J. Murray, The Physics of Microfabrication, Plenum Press, 1982.

14. Machining Profiles
FIGURE Machining profiles associated with different dry-etching techniques: (a) sputtering; (b) chemical; (c) ion-enhanced energetic; (d) ion-enhanced inhibitor. Source: After M. Madou.

15. Reactive Plasma Etching
FIGURE (a) Schematic illustration of reactive plasma etching. (b) Example of deep reactive ion etched trench. Note the periodic undercuts, or scalloping. (c) Near vertical sidewalls produced through DRIE with an anisotropic etching process. (d) An example of cryogenic dry etching, showing a145µm deep structure etched into Si using a 2.0µm thick oxide masking layer. The substrated temperature was -140˚C during etching. Source: (a) AfterM. Madou. (b)-(d) R. Kassing and I. W. Rangelow, University of Kassel.

16. Holes Generated From a Square Mask
FIGURE Different holes generated from a square mask in (a) isotropic (wet) etching; (b) ODE with a larger hole; (d) ODE of a rectangular hole; (e) deep reactive ion etching; (f) vertical etching. Source: After M. Madou.

17. Two-Level Metal Interconnect
FIGURE (a) Scanning electron microscope photograph of a two-level metal interconnect. Note the varying surface topography. (b) Schematic drawing of a two-level metal interconnect structure. Source: R.C. Jaeger.

18. Defect Probe
FIGURE A probe checks for defects, and an ink mark is placed on defective dice. Source: Intel Corp.

19. Wire Bonds Connecting Package Leads
FIGURE (a) SEM photograph of wire bonds connecting package leads (left-hand side) to die bonding pads. (b) and (c) Detailed views of (a). Source: Courtesy of Micron Technology, Inc.

20. IC Packages
FIGURE Schematic illustration of different IC Packages: (a) dual in-line (DIP); (b) ceramic flat pack; (c) common surface-mount configurations; (d) ball-grid array (BGA). Source: After R.C. Jaeger, A.B. Glaser, and G. E. Subak-Sharpe.

21. Flip-Chip Technology
FIGURE Illustration of flip-chip technology. (a) Flip-chip package with solder plated metal balls and pads on the printed circuit board; (b) flux application and placement; (c) reflow soldering; (d) encapsulation. Source: Paul Wright, 21st Century Manufacturing, Upper Saddle River, NJ: Prentice Hall, 2001.

22. Circuit Board Structures
FIGURE Types of circuit board structures: (a) single sided; (b) double sided; (c) multilayer, showing vias and pathways between layers. Source: M. Groover, Fundamentals of Modern Manufacturing. Upper Saddle River, NJ: Prentice Hall, 1996.

23. Design Features of Circuit Boards
FIGURE Design features in printed circuit boards. Source: M. Groover, Fundamentals of Modern Manufacturing, Upper Saddle River, NJ: Prentice Hall, 1996.

24. Layout of IC Packages on Circuit Boards
FIGURE Layout of IC packages and other components on circuit boards to facilitate wave soldering. Source: After G, Boothroyd, P. Dewhurst, and W. Knight, Product Design for Manufacture and Assembly, Marcel-Dekker, 1994.

25. Bulk Micromachining
FIGURE Schematic illustration of bulk micromachining. (a) Diffuse dopant in desired pattern . (b) Deposit and pattern masking film. (c) Orientation-dependent etch, leaving behind a freestanding structure. Source: K.R. Williams, Agilent Laboratories.

26. Steps in Surface Microma-chining
FIGURE Schematic illustration of the steps in surface micromachining: (a) deposition of a phosphosilicate glass (PSG) spacer later; (b) etching of the spacer layer; (C) deposition of polysilicon; (d) etching of polysilicon; (e) selective wet etching of PSG, leaving the silicon substrate and deposited polysilicon unaffected.

27. Microlamp
FIGURE A microclamp produced form a combination of bulk and surface micromachining. Source: K.R. Williams, Agilent Technologies.

28. Deployed Micromirror
FIGURE (a) SEM image of deployed micromirror. (b) Detail of the micromirror hinge. Source: Sandia National Laboratories.

29. Hinge Manufacture
FIGURE Schematic illustration of the steps required to manufacture a hinge. (a) Deposition of a phosphosilicate glass (PSG) spacer later and polysilicon layer. (See Fig ) (b) Deposition of a second spacer layer. (c) Selective etching of the PSG. (d) Depostion of polysilicon to form a staple for the hinge. (e) After selective wet etching of the PSG, the hinge can rotate.

30. Thermal Ink-Jet Printer Operation Sequence
FIGURE Sequence of operation of a thermal ink-jet printer. (a) Resistive heating element is turned on , rapidly vaporizing ink and forming a bubble. (b) Within five microseconds, the bubble has expanded and displaced liquid ink from the nozzle. (c) Surface tension breaks the ink stream in to a bubble, which is discharged at high velocity. The heating element is turned off at this time, so that the bubble collapses as heat is transferred to the surrounding ink. (d) within 24 microseconds, and ink droplet (and undesirable satellite droplets) are ejected, and surface tension of the ink draws more liquid form the reservoir. Source: From F. G. Tseng, “Microdroplet Generators,” in M. Gad-el-hak (ed.), The MEMS Handbook, CRC Press, 2002.

31. Sequence for Producing Thermal Ink-Jet Printer Heads
FIGURE The manufacturing sequence for producing thermal ink-jet printer heads. Source: From F. G. Tseng, “Microdroplet Generators,” in M. Gad-el-hak (ed.), The MEMS Handbook, CRC Press, 2002.

32. Electroformed Nickel Structures
FIGURE (a) Electroformed 200-µm-tall nickel structures. (b) Detail of 5-µm-wide nickel lines and spaces. Source: After Todd Christenson, The MEMS Handbook, CRC Press, 2002.

33. Multilevel Fabrication Through Diffusion Bonding
FIGURE (a) Multilevel MEMS fabrication through wafer-scale diffusion bonding. (b) A suspended ring structure for measurement of tensile strain, formed by two-layer wafer-scale diffusion bonding. Source: After T. Christenson, Sandia National Laboratories.

34. Micro-Acceleration Sensor
FIGURE Schematic illustration of a micro-acceleration sensor. Source: After N. Maluf.