1. Diseño de Lógica Secuencial Sincrónica (2)

2. Registro de Desplazamiento en VHDL: SI/SO
library ieee;
use ieee.std_logic_1164.all;
entity shift_si_so_x4 is
port(
clk,clr : in std_logic;
serial_in : in std_logic;
serial_out: out std_logic);
end shift_si_so_x4;
architecture behav of shift_si_so_x4 is
signal data_out_temp: std_logic_vector(3 downto 0);
begin
shift_proc: process(clk, clr)
if (clr = '0') then
data_out_temp <= others(=>'0‘);
elsif (rising_edge(clk)) then
data_out_temp <= data_out_temp(2 downto 0) & serial_in;
end if;
end process;
data_out <= data_out_temp(3);
end behave;
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3. Registro de Desplazamiento en VHDL: SI/PO
library ieee;
use ieee.std_logic_1164.all;
entity shift_pi_po_x8 is
port(
clk,clr : in std_logic;
serial_in : in std_logic;
paralel_out: out std_logic_vector(8 downto 0);
end shift_pi_po_x8;
architecture behav of shift_si_so_x4 is
signal data_out_temp: std_logic_vector(3 downto 0);
begin
shift_proc: process(clk, clr)
if (clr = '0') then
data_out_temp <= others(=>'0‘);
elsif (rising_edge(clk)) then
data_out_temp <= data_out_temp(3 downto 1) & serial_in;
end if;
end process;
data_out <= data_out_temp;
end behave;
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4. Registro de Desplazamiento en VHDL: 74x194
-- example of a 4-bit shift register -- LS194 4-bit bidirectional universal shift register library ieee; use ieee.std_logic_1164.all; entity shift_74x194 is port( clk,clr_n,s0,s1,lin,rin: in std_logic; paralel_in : in std_logic_vector(3 downto 0); q : out std_logic_vector(3 downto 0) ); end shift_74x194 ;
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5. Registro de Desplazamiento en VHDL: 74x194
architecture behav of shift_74x194 is signal temp_q: std_logic_vector(3 downto 0); signal ctrl : std_logic_vector(1 downto 0); begin ctrl <= s0 & s1; shift_proc: process(clk, clr_n) if (clr_n = '0') then temp_q <= (others => '0'); elsif (rising_edge(clk)) then case ctrl is when "11" => temp_q <= paralel_in; when "10" => temp_q <= rin & temp(3 downto 1); when "01" => temp_q <= temp(2 downto 0) & lin; when others => temp_q <= temp_q; end case; end if; end process; q <= temp_q; end behav;
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6. Contadores
Flip-flops pueden ser conectados juntos para realizar operaciones de cuenta. Este tipo de estructura se denomina contador
El numero de flip-flops usados y el modo en que ellos están conectados determinan el módulo (cantidad de estados) del contador, y la secuencia de la cuenta de cada ciclo de cuenta
Contador sincrónico significa que todos los flip-flops son controlados por una misma señal de reloj
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7. Contadores MSI
El contador comercial mas popular es el 74x163, contador binario de 4 bits, con entradas activas en bajo de carga y reset
The most popular MSI counter is the 74x163, a synchronous 4-bit binary counter with active-low load and clear inputs, with the traditional logic symbol shown in Figure Its function is summarized by the state table in Table 8-11, and its internal logic diagram is shown in Figure The ’163 uses D flip-flops rather than T flip-flops internally to facilitate the load and clear functions. Each D input is driven by a 2-input multiplexer consisting of an OR gate and two AND gates. The multiplexer output is 0 if the CLR_L input is asserted. Otherwise, the top AND gate passes the data input (A, B, C, or D) to the output if LD_L is asserted. If neither CLR_L nor LD_L is asserted, the bottom AND gate passes the output of an XNOR gate to the multiplexer output The XNOR gates perform the counting function in the ’163. One input of each XNOR is the corresponding count bit (QA, QB, QC, or QD); the other input is 1, which complements the count bit, if and only if both enables ENP and ENT are asserted and all of the lower-order count bits are 1. The RCO (“ripple carry out”) signal indicates a carry from the most significant bit position, and is 1 when all of the count bits are 1 and ENT is asserted
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8. 74x163 Reset: sinc/asinc? Load: sinc/asinc?
The most popular MSI counter is the 74x163, a synchronous 4-bit binary counter with active-low load and clear inputs, with the traditional logic symbol shown in Figure Its function is summarized by the state table in Table 8-11, and its internal logic diagram is shown in Figure The ’163 uses D flip-flops rather than T flip-flops internally to facilitate the load and clear functions. Each D input is driven by a 2-input multiplexer consisting of an OR gate and two AND gates. The multiplexer output is 0 if the CLR_L input is asserted. Otherwise, the top AND gate passes the data input (A, B, C, or D) to the output if LD_L is asserted. If neither CLR_L nor LD_L is asserted, the bottom AND gate passes the output of an XNOR gate to the multiplexer output The XNOR gates perform the counting function in the ’163. One input of each XNOR is the corresponding count bit (QA, QB, QC, or QD); the other input is 1, which complements the count bit, if and only if both enables ENP and ENT are asserted and all of the lower-order count bits are 1. The RCO (“ripple carry out”) signal indicates a carry from the most significant bit position, and is 1 when all of the count bits are 1 and ENT is asserted
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9. Contador Libre (free running counter)
Even though most MSI counters have enable inputs, they are often used in a free-running mode in which they are enabled continuously. Figure 8-32 shows the connections to make a ’163 operate in this way, and Figure 8-33 shows the resulting output waveforms. Notice that starting with QA, each signal has half the frequency of the preceding one. Thus, a free-running ’163 can be used as a divide-by-2, -4, -8, or -16 counter, by ignoring any unnecessary high-order output bits. Note that the ’163 is fully synchronous; that is, its outputs change only on the rising edge of CLK. Some applications need an asynchronous clear function as provided by the 74x161. The ’161 has the same pinout as the ’163, but its CLR_L input is connected to the asynchronous clear inputs of its flip-flops
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10. Contador de Módulo ????
Aunque el 74x163 es un contador de módulo 16, puede ser usado para que cuente en un módulo menor que 16 usando las entradas CLR o LD para cambiar la secuencia de cuenta normal
Although the ’163 is a modulo-16 counter, it can be made to count in a modulus less than 16 by using the CLR_L or LD_L input to shorten the normal counting sequence. For example, Figure 8-35 shows one way of using the ’163 as a modulo-11 counter. The RCO output, which detects state 15, is used to force the next state to 5, so that the circuit will count from 5 to 15 and then start at 5 again, for a total of 11 states per counting cycle
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11. Contador de Modulo ???
A different approach for modulo-11 counting with the ’163 is shown in Figure This circuit uses a NAND gate to detect state 10 and force the next state to 0. Notice that only a 2-input gate is used to detect state 10 (binary 1010).
Although a 4-input gate would normally be used to detect the condition CNT10 = Q3 ⋅ Q2′ ⋅ Q1 ⋅ Q0′, the 2-input gate takes advantage of the fact that no other state in the normal counting sequence of 0–10 has Q3 = 1 and Q1 = 1. In general, to detect state N in a binary counter that counts from 0 to N, we need to AND only the state bits that are 1 in the binary encoding of N
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12. Cual es la secuencia de este contador?
El 74x153 usado como un contador BCD Exceso de 3
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13. Cual es la secuencia de este contador?
El 74x163 usado como un contador BCD Exceso de 3
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14. Conectando Contadores en Cascada
Cómo puede conectar dos contadores de 4 bits para formar uno de 8 ?
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15. Estados Decodificados de un Contador
Dado el siguiente circuito:
- Cuál es el módulo del contador?
- Que indican las salidas del decodificador?
A binary counter may be combined with a decoder to obtain a set of 1-out-of-mcoded signals, where one signal is asserted in each counter state. This is useful when counters are used to control a set of devices where a different device is enabled in each counter state. In this approach, each output of the decoder enables a different device.
Figure 8-42 shows how a 74x163 wired as a modulo-8 counter can be combined with a 74x138 3-to-8 decoder to provide eight signals, each one representing a counter state. Figure 8-43 shows typical timing for this circuit.
Each decoder output is asserted during a corresponding clock period.
Notice that the decoder outputs may contain “glitches” on state transitions where two or more counter bits change, even though the ’163 outputs are glitch free and the ’138 does not have any static hazards. In a synchronous counter like the ’163, the outputs don’t change at exactly the same time. More important
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16. Estados Decodificados de un Contador
Glitches
Figure 8-43 shows typical timing for this circuit.
Each decoder output is asserted during a corresponding clock period.
Notice that the decoder outputs may contain “glitches” on state transitions where two or more counter bits change, even though the ’163 outputs are glitch free and the ’138 does not have any static hazards. In a synchronous counter like the ’163, the outputs don’t change at exactly the same time. More important multiple signal paths in a decoder like the ’138 have different delays; for example, the path from B to Y1_L is faster than the path from A to Y1_L. Thus, even if the input changes simultaneously from 011 to 100, the decoder may behave as if the input were temporarily 001, and the Y1_L output may have a glitch. In the present example, it can be shown that the glitches can occur in any realization of the binary decoder function; this problem is an example of a function hazard. In most applications, the decoder output signals portrayed in Figure 8-43 would be used as control inputs to registers, counters, and other edge-triggered devices (e.g., EN_L in a 74x377, LD_L in a 74x163, or ENP_L in a 74x169). In such a case, the decoding glitches in the figure are not a problem, since they occur after the clock tick. They are long gone before the next tick comes along, when the decoder outputs are sampled by other edge-triggered devices. However, the glitches would be a problem if they were applied to something like the S_L or R_L inputs of an S-R latch. Likewise, using such potentially glitch signals as clocks for edge-triggered devices is a definite no-no
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17. Salidas Glitch-Free del Contador + Deco
If necessary, one way to “clean up” the glitches in Figure 8-43 is to connect the ’138 outputs to another register that samples the stable decoded outputs on the next clock tick, as shown in Figure Notice that the decoded outputs have been renamed to account for the 1-tick delay through the register. However, once you decide to pay for an 8-bit register, a less costly solution is to use an 8-bit “ring counter,” which provides glitch-free decoded outputs directly, as we’ll show in Section
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18. Contadores en VHDL library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_nbits is
generic(cnt_w: natural:= 4)
port (
-- clock & reset inputs
clk : in std_logic;
rst : in std_logic;
-- ouptuts
count : out std_logic_vector(cnt_w-1 downto 0));
end counter_nbits;
architecture rtl of counter_nbits is
-- signal declarations
signal count_i: unsigned(cnt_w-1 downto 0);
begin
count_proc: process(clk, rst)
if(rst='0') then
count_i <= (others => '0'); elsif(rising_edge(clk)) then
count_i <= count_i + 1;
end process count_proc;
count <= std_logic_vector(count_i);
end architecture rtl;
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19. Contador Up/Down en VHDL
architecture rtl of counter_ud is
-- signal declarations
signal count_i: unsigned(cnt_w-1 downto 0);
begin
count_proc: process(clk, rst)
if(rst='0') then
count_i <= (others => '0'); elsif(rising_edge(clk)) then
if(up_dw = '1') then -- up
count_i <= count_i + 1;
else down
count_i <= count_i - 1;
end if;
end process count_proc;
count <= std_logic_vector(count_i);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_ud is
generic(cnt_w: natural:= 4)
port (
-- clock & reset inputs
clk : in std_logic;
rst : in std_logic;
-- control input signals
up_dw : in std_logic;
-- ouptuts
count : out std_logic_vector(cnt_w-1 downto 0));
end counter_ud;
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20. Contador Up/Down en VHDL - Enteros
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_ud_i is
generic(cnt_w: natural:= 4)
port (
-- clock & reset inputs
clk : in std_logic;
rst_n : in std_logic;
-- control input signals
up_dw : in std_logic;
-- ouptuts
count : out std_logic_vector(cnt_w-1 downto 0));
end counter_ud_i;
architecture rtl of counter_ud_i is
begin
count_proc: process(clk, rst)
variable count_i: integer range 0 to 255;
if(rst_n = '0') then
count_i := 0;
elsif(rising_edge(clk)) then
if(count_i = 255) then
else
count_i := count_i + 1;
end if;
end process count_proc;
count <= std_logic_vector(to_unsigned(count_i,8));
end architecture rtl;
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21. Contador Up/Down en VHDL - Enteros
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_ud_i is
generic(cnt_w: natural:= 4)
port (
-- clock & reset inputs
clk : in std_logic;
rst_n : in std_logic;
-- control input signals
up_dw : in std_logic;
-- ouptuts
count : out std_logic_vector(cnt_w-1 downto 0));
end counter_ud_i;
architecture rtl of counter_ud_i is
begin
count_proc: process(clk, rst)
variable count_i: integer range 0 to 199;
if(rst_n = '0') then
count_i := 0;
elsif(rising_edge(clk)) then
if(count_i = 200) then
else
count_i := count_i + 1;
end if;
end process count_proc;
count <= std_logic_vector(to_unsigned(count_i,8));
end architecture rtl;
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22. Sistemas Sincrónicos – Diagrama de Tiempo
Figure 8-1 shows a fairly typical timing diagram that specifies the requirements and characteristics of input and output signals in a synchronous circuit.
The first line shows the system clock and its nominal timing parameters. The remaining lines show a range of delays for other signals.
For example, the second line shows that flip-flops change their outputs at some time between the rising edge of CLOCK and time tffpd afterward. External circuits that sample these signals should not do so while they are changing. The timing diagram is drawn as if the minimum value of tffpd is zero; a complete documentation package would include a timing table indicating the actual minimum, typical, and maximum values of tffpd and all other timing parameters. The third line of the timing diagram shows the additional time, tcomb , required for the flip-flop output changes to propagate through combinational logic elements, such as flip-flop excitation logic. The excitation inputs of flipflops and other clocked devices require a setup time of tsetup, as shown in the fourth line. For proper circuit operation we must have tclk - tffpd - tcomb > tsetup . Timing margins indicate how much “worse than worst-case” the individual components of a circuit can be without causing the circuit to fail. Well-designed systems have positive, nonzero timing margins to allow for unexpected circumstances (marginal components, brown-outs, engineering errors, etc.) and clock skew (Section 8.8.1)
tclk > tsetup + tffpd + tcomb
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23. Sistemas Sincrónicos – Diagrama de Tiempo
En los sistemas sincrónicos, los diagramas de tiempo muestran la relación entre el reloj, las entradas, salidas y señales internas
Figure 8-1 shows a fairly typical timing diagram that specifies the requirements and characteristics of input and output signals in a synchronous circuit.
The first line shows the system clock and its nominal timing parameters. The remaining lines show a range of delays for other signals.
For example, the second line shows that flip-flops change their outputs at some time between the rising edge of CLOCK and time tffpd afterward. External circuits that sample these signals should not do so while they are changing. The timing diagram is drawn as if the minimum value of tffpd is zero; a complete documentation package would include a timing table indicating the actual minimum, typical, and maximum values of tffpd and all other timing parameters. The third line of the timing diagram shows the additional time, tcomb , required for the flip-flop output changes to propagate through combinational logic elements, such as flip-flop excitation logic. The excitation inputs of flipflops and other clocked devices require a setup time of tsetup, as shown in the fourth line. For proper circuit operation we must have tclk - tffpd - tcomb > tsetup . Timing margins indicate how much “worse than worst-case” the individual components of a circuit can be without causing the circuit to fail. Well-designed systems have positive, nonzero timing margins to allow for unexpected circumstances (marginal components, brown-outs, engineering errors, etc.) and clock skew (Section 8.8.1)
Para el buen funcionamiento del circuito se debe cumplir:
tclk - tffpd - tcomb > tsetup
tclk > tsetup + tffpd + tcomb
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24. Señal de Reloj – Sistema Secuencial
Sí la lógica secuencial cambia con el Flanco Positivo de Reloj
The state changes of most sequential circuits occur at times specified by a free-running clock signal. Figure 7-1 gives timing diagrams and nomenclature for typical clock signals. By convention, a clock signal is active high if state changes occur at the clock’s rising edge or when the clock is HIGH, and active low in the complementary case. The clock period is the time between successive transitions in the same direction, and the clock frequency is the reciprocal of the period. The first edge or pulse in a clock period or sometimes the period itself is called a clock tick. The duty cycle is the percentage of time that the clock signal is at its asserted level. Typical digital systems, from digital watches to supercomputers, use a quartz-crystal oscillator to generate a free-running clock signal.
Clock frequencies might range from kHz (for a watch) to 500 MHz (for a CMOS RISC microprocessor with a cycle time of 2 ns); “typical” systems using TTL and CMOS parts have clock frequencies in the 5–150 MHz range.
In this chapter we’ll discuss two types of sequential circuits that account for the majority of practical discrete designs. A feedback sequential circuit uses ordinary gates and feedback loops to obtain memory in a logic circuit, thereby creating sequential-circuit building blocks such as latches and flip-flops that are used in higher-level designs. A clocked synchronous state machine uses these
building blocks, in particular edge-triggered D flip-flops, to create circuits whose inputs are examined and whose outputs change in accordance with a controlling clock signal. There are other sequential circuit types, such as general fundamental mode, multiple pulse mode, and multiphase circuits, which are sometimes useful in high-performance systems and VLSI, and are discussed in advanced texts
Periodo del Reloj: tiempo entre sucesivas transiciones del flanco activo
Frecuencia del Reloj: es la inversa del periodo de reloj
Ciclo de Trabajo (duty cycle): porcentaje de tiempo que la señal de reloj está en su valor activo
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25. Señal de Reloj – Sistema Secuencial
Sí la lógica secuencial cambia con el Flanco Negativo de Reloj
The state changes of most sequential circuits occur at times specified by a free-running clock signal. Figure 7-1 gives timing diagrams and nomenclature for typical clock signals. By convention, a clock signal is active high if state changes occur at the clock’s rising edge or when the clock is HIGH, and active low in the complementary case. The clock period is the time between successive transitions in the same direction, and the clock frequency is the reciprocal of the period. The first edge or pulse in a clock period or sometimes the period itself is called a clock tick. The duty cycle is the percentage of time that the clock signal is at its asserted level. Typical digital systems, from digital watches to supercomputers, use a quartz-crystal oscillator to generate a free-running clock signal.
Clock frequencies might range from kHz (for a watch) to 500 MHz (for a CMOS RISC microprocessor with a cycle time of 2 ns); “typical” systems using TTL and CMOS parts have clock frequencies in the 5–150 MHz range.
In this chapter we’ll discuss two types of sequential circuits that account for the majority of practical discrete designs. A feedback sequential circuit uses ordinary gates and feedback loops to obtain memory in a logic circuit, thereby creating sequential-circuit building blocks such as latches and flip-flops that are used in higher-level designs. A clocked synchronous state machine uses these building blocks, in particular edge-triggered D flip-flops, to create circuits whose inputs are examined and whose outputs change in accordance with a controlling clock signal. There are other sequential circuit types, such as general fundamental mode, multiple pulse mode, and multiphase circuits, which are sometimes useful in high-performance systems and VLSI, and are discussed in advanced texts
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26. Problemas con el Reloj – Desfasaje de Reloj
Sistemas sincrónicos que usan flip-flops disparados por flanco operan sin problemas si todos los flip-flop reciben el flanco al mismo tiempo
Pero la realidad es otra, por ejemplo qué pasa en este caso?
Synchronous systems using edge-triggered flip-flops work properly only if all flip-flops see the triggering clock edge at the same time. Figure 8-85 shows what can happen otherwise. Here, two flip-flops are theoretically clocked by the same signal, but the clock signal seen by FF2 is delayed by a significant amount relative to FF1’s clock. This difference between arrival times of the clock at different devices is called clock skew
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27. Problemas con el Reloj – Desfasaje de Reloj
Clock skew is the Spatial separation in clock edges between different nodes in a given cycle
We’ve named the delayed clock in Figure 8-85(a) “CLOCKD.” If FF1’s propagation delay from CLOCK to Q1 is short, and if the physical connection of Q1 to FF2 is short, then the change in Q1 caused by a CLOCK edge may actually reach FF2 before the corresponding CLOCKD edge. In this case, FF2 may go to an incorrect next state determined by the next state of FF1 instead of the current state, as shown in (b). If the change in Q1 arrives at FF2 only slightly early relative to CLOCKD, then FF2’s hold-time specification may be violated, in which case FF2 may become metastable and produce an unpredictable output. If Figure 8-85 reminds you of the essential hazard shown in Figure 7-101, you’re on to something. The clock-skew problem may be viewed simply as a manifestation of the essential hazards that exist in all edge-triggered devices. We can determine quantitatively whether clock skew is a problem in a given system by defining tskew to be the amount of clock skew and using the other timing parameters defined in Figure 8-1. For proper operation, we need tffpd(min) + tcomb(min) - thold - tskew(max) > 0 In other words, clock skew subtracts from the hold-time margin that we defined in Section
Desfasaje de Reloj = Clock Skew
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28. Fluctuaciones del Reloj - Clock Jitter
Variación temporal de la señal de reloj que se manifiesta como la incertidumbre en el tiempo de flancos consecutivos del periodo de un reloj
Clock Jitter represents the inaccuracy in clock edges at the same point at different times Jitter applies to the same clock or separate clocks originating from the same or different sources, Jitter is in addition to clock skew
Another imperfection, a bit beyond the scope of this text, is “clock jitter.” A 10-MHz clock does not have a period of exactly 100 ns on every cycle—it may be ns in one cycle, and ns in the next. This is not a big deal in such a slow circuit, but in a 500-MHz circuit, the same 0.1 ns of jitter eats up 5% of the 2-ns timing budget. And the jitter in some clock sources is even higher!
Temporal variation of the clock signal manifested as uncertainty of consecutive edges of a periodic clock signal.
It is caused by temporal noise events
Manifested as:
- cycle-to-cycle or short-term jitter, tJS
- long-term jitter, tJL
Mainly characteristic of clock generation system
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29. Incertidumbres de la Señal de Reloj
Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic
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30. Entradas Asincrónicas
Sistemas digitales de todo tipo si o si tienen que lidiar con señales de entrada asincrónicas que no están sincronizadas con el reloj del sistema
Entradas asincrónicas pueden provenir de diversas fuentes, por ej.: teclado, llave, pulsador, sensor, salida de otro CI (con distinta señal de reloj), etc.
Even though it is theoretically possible to build a computer system that is fully synchronous, you couldn’t do much with it, unless you can synchronize your keystrokes with a 500 MHz clock. Digital systems of all types inevitably must deal with asynchronous input signals that are not synchronized with the system clock.
Asynchronous inputs are often requests for service (e.g., interrupts in a computer) or status flags (e.g., a resource has become available). Such inputs normally change slowly compared to the system clock frequency, and need not be recognized at a particular clock tick. If a transition is missed at one clock tick, it can always be detected at the next one. The transition rates of asynchronous signals may range from less than one per second (the keystrokes of a slow typist) to 100 MHz or more (access requests for a 500-MHz multiprocessor system’s shared memory).
Ignoring the problem of metastability, it is easy to build a synchronizer, a circuit that samples an asynchronous input and produces an output that meets the setup and hold times required in a synchronous system. As shown in Figure 8-91, a D flip-flop samples the asynchronous input at each tick of the system clock and produces a synchronous output that is valid during the next clock period.
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31. Entradas Asincrónicas - Sincronizadores
EL sincronizador mas básico, es un flip-flop D que muestrea la señal de entrada asincrónica en cada flanco del reloj, y produce una salida sincrónica que es valida durante el próximo ciclo de reloj.
Ignoring the problem of metastability, it is easy to build a synchronizer, a circuit that samples an asynchronous input and produces an output that meets the setup and hold times required in a synchronous system. As shown in Figure 8-91, a D flip-flop samples the asynchronous input at each tick of the system clock and produces a synchronous output that is valid during the next
clock period.
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32. Sincronizador Recomendado
Inputs to flip-flop FF1 are asynchronous with the clock, and may violate the flip-flop’s setup and hold times. When this happens, the META output may become metastable and remain in that state for an arbitrary time. However, we assume that the maximum duration of metastability after the clock edge is tr. (We show how to calculate the probability that our assumption is correct in the next subsection.) As long as the clock period is greater than tr plus the FF2’s setup time, SYNCIN becomes a synchronized copy of the asynchronous input on the next clock tick without ever becoming metastable itself. The SYNCIN signal is distributed as required to the rest of the system.
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33. Sincronizador en VHDL library ieee; use ieee.std_logic_1164.all;
entity synchronizer is
port(
clk : in std_logic;
asyncin : in std_logic;
syncin : out std_logic);
end synchronizer;
architecture behave of synchronizer is
signal sync_temp: std_logic;
begin
sync_proc: process(clk)
if (rising_edge(clk)) then
sync_temp <= asyncin;
syncin <= sync_temp;
end if;
end process;
end behave;
Inputs to flip-flop FF1 are asynchronous with the clock, and may violate the flip-flop’s setup and hold times. When this happens, the META output may become metastable and remain in that state for an arbitrary time. However, we assume that the maximum duration of metastability after the clock edge is tr. (We show how to calculate the probability that our assumption is correct in the next subsection.) As long as the clock period is greater than tr plus the FF2’s setup time, SYNCIN becomes a synchronized copy of the asynchronous input on the next clock tick without ever becoming metastable itself. The SYNCIN signal is distributed as required to the rest of the system.
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