1. EECE6017C Lab 1 Introduction to Altera tools and Circuit Simulation
Prelab Activities:
ORDER a DE0-Nano-SOC board by Monday August 29
Make sure you finish all Lab 0 assignments before working on lab 1
Download and install Quartus II package, Verilog (latest version). Do not do this in lab, it takes a while.
Refer to DE0-Nano-Soc Getting Started Guide.pdf attached along with the lab manual for USB driver installation for your computer and basics about using the board
Finish homework - 4 bit Adder and 4 bit shifter; fsm transition diagram and state table
Work to be done during this lab:
Questions on tools / Verilog: come up with questions if there are any—post them on discussion board
Work on the behavioral implementation of the ALU discussed below. This will be due in Lab 2.
Continue to work on learning the Altera tools and tutorials listed in the websites.

2. Lab Instructions
Your task is to implement the ALU design described below. You need to do the following:
Write a well-structured, well-commented Verilog program to implement the circuit on the Altera board, using built-in I/O devices.
Write a well-designed test set for your program. Explain why your test set is sufficient to test your circuit.
Implement your design in Quartus and simulate it in Modelsim; when it is working, download it on the board so you can demonstrate its correct behavior.
Turn in at the beginning of the next lab:
the Verilog program listing and the i/o definitions (well-commented, well-displayed)
the test bench program and your explanation for why it is sufficient (just list inputs and outputs, DO NOT turn in wave forms)
The basic implementation info (# LUTs & #ffs used, timing, etc.)
A summary of any inputs for which the ALU circuit is not giving correct results and any ideas you have about what the problem is
A short paragraph describing any difficulties you encountered in completing this assignment

3. Combinational Circuit and Sequential Circuit
1. Design and test the following combinational logic structures using behavioral model. Using the full adders designed in the previous lab, create a 4-bit Multiplier that takes in two 4-bit unsigned values. It has a single 8-bit unsigned output. Implement the 4-bit multiplier that uses the addition of partial products method. Testing: Test the adder both in simulation and on the board. To test the adder on the board, hook your 4- bit adder inputs to four input switches on the DE0-Nano-SOC board; hook the outputs to five LEDs on the board. Use the push button to load every 4-Bit inputs, (i.e.,) Load A (3:0) using Switch and press the push button to Load B in the switch. If you did not have the board yet, simulate the circuit and show the graphical output in waveform editor. Be sure to show the demo in the De0 board once you get it.
Example

4. ALU Design * - Refer to Slide 5
2. Design a BEHAVIORAL implementation for ALU as explained below.
The ALU has three inputs: two 4-bit signed values and a 4-bit control signal that determines which operation the ALU should perform. The ALU has a single 4-bit signed output (plus a carry-out for the adder) which is the result of the operation. The ALU can perform ten operations as per the table below.
The ALU should instantiate a single 4-bit adder (also used for subtract), and a left/right shifter. Use the outputs from these modules and some combinational logic to generate all ten possible values. Finally, use a multiplexer to select the correct signal.
Simulate the ALU output in Quartus and show the final result using the LEDs in the DE0-Nano board.
Description
Instruction
Control S[3:0]
Addition
ADD
0100
Subtraction
SUB
0101
Bitwise NOT
NOT
1000
Bitwise OR OR
1001
Bitwise AND
AND
1010
Bitwise XOR
XOR
1011
Shift LEFT
SLL
1100
Shift RIGHT
SRL
1101
Shift Right Arithmetic*
SRA
1110
Pass A Through
CPY
1111
* - Refer to Slide 5

5. Points to remember while implementing:
If any control signal other those specified is given to the ALU, the ALU should set all 8 output bits to zero.
The NOT operation returns the logical inverse of the first ALU input, and it ignores the second input
The SUB operation computes output = A - B.
For the shift operations, A is the value to be shifted and the four lower bits of B determine the amount of the shift (0 to 4 binary digits).
The arithmetic shift right* performs sign extension; in contrast, the logical shift right performs zero extension.
Homework
Design a 3 bit Counter (Finite State Machine), use the state diagram and transition table for reference.
Design a FSM for Traffic light controller (see Lab 2 manual for design guidelines) - Due beginning of next lab. Design FSM includes coming up with number of states in FSM, state diagram and state transition table. SEE NEXT SLIDE FOR DETAILS.
Hints:
State diagram for 3 bit counter
State transition table

6. Traffic Light Controller
Your task is to design a controller for a traffic light. (No implementation—that will be the lab for NEXT WEEK). You will need to observe a real traffic light (safely) to see how the light works so that you can make an accurate controller. Your light should be at the intersection of 2 streets and should have at least one left turn signal and one walk pushbutton.
You must include all lights, turn signals, and walk signals.
You must include an “emergency / broken” state when the light becomes a “4-way stop”.
You must include a “fire” state when the light flashes yellow on one street and red on the other street.
You must include a “manual” state where a pushbutton controls the light cycle.
You must make sure that the change from one state to another is not instantaneous, i.e., when the light turns red in one direction, it does not immediately turn green in the perpendicular direction. (For a demo, you will want to make the time in each state relatively short, but you still need to have “transitions” between states for safety. Your design document should tell how long the controller will stay in each state under normal operating conditions.)
You must change modes using a pushbutton:
Normal operation
Left turn
Walk (?)
Emergency
Fire
Manual
You must display all states as patterns using the board LEDs (note: you can get more states by allowing blinking lights or constant lights).
NOTE: this week, just derive the specifications. The Verilog implementation will be assigned next week.

7. Quartus II Report generation
Collect Report from Summary, Resource Usage summary, Post-Synthesis Netlist Statistics
Right Click->Export and the report will be saved with .RPT file format under the project folder

8. Shift Right Arithmetic
In an arithmetic right shift (ARSH), the sign bit is shifted in on the left, thus preserving the sign of the operand. In all other shifts, zeroes are shifted in as needed. Here are a few examples: Left Shift (LSH) 1 bit: unsigned char x = x << 1; Before: ( = 8 decimal) After: ( = 16 decimal ) Before: After: ( one bit is "lost" off the top) Logical Right Shift (RSH) 1 bit: unsigned char x = x >> 1; Before: ( = 8 decimal ) After: ( = 4 decimal ) Before: After: ( one bit is "lost" off the bottom ) Before: ( = 129 decimal ) After: ( = 64 decimal - one bit is "lost" off the bottom ) Arithmetic Left Shift: There is no Arithmetic Left Shift because it would work just the same as a Logical Left Shift - use a Logical Left Shift instead. Arithmetic Right Shift (ARSH) 1 bit: signed char x = x >> 1; (Note: In C language, right shifts may or may not be arithmetic!) Before: ( = -125 decimal in two's complement ) After: ( = -63 decimal - one bit is "lost" off the bottom ) After: ( = -32 decimal - one bit is "lost" off the bottom ) After: ( = -16 decimal ) After: ( = -8 decimal ) After: ( = -4 decimal ) After: ( = -2 decimal ) After: ( = -1 decimal ) After: ( = -1 decimal - one bit is "lost" off the bottom )

9. The "Right Shift (Arithmetic)" is useful when used on twos-complement numbers. The sign bit (leftmost bit) is replicated at the high end of the
number, instead of bringing in zeroes as with "Right Shift (Logical)". If the number is negative, replicating the sign bit with "Right Shift (Arithmetic)"
keeps it negative.
Look at the 8-bit binary bit patterns below and note the differences between Arithmetic Right Shift and Logical Right Shift:
(-9) arithmetic-right-shifted gives (-5)
logical-right-shifted gives (+123)
(-5) arithmetic-right-shifted gives (-3)
logical-right-shifted gives (+125)
(-3) arithmetic-right-shifted gives (-2)
logical-right-shifted gives (+126)
(-2) arithmetic-right-shifted gives (-1)
logical-right-shifted gives (127)
(-1) arithmetic-right-shifted gives (-1)
logical-right-shifted gives (+127)
(+127) arithmetic-right-shifted gives (+63)
logical-right-shifted gives (+63)
(+1) arithmetic-right-shifted gives (0)
logical-right-shifted gives (0)
Note that the Arithmetic shift (instead of the Logical) only makes a difference if the sign bit is on before the shift
Reference: