Advanced Digital Design

Advanced Digital Design
Asynchronous Design: Principles by A. Steininger and M. Delvai Vienna University of Technology

© A. Steininger & M. Delvai / TU Vienna
recall Previous Conclusion The purpose of a design style is to provide information for flow control. Boolean Logic alone cannot provide this information. Severe technological problems force us to question the current (synchronous) design practice. We shall focus on that. Alternatives must be evaluated very critically with respect to improvements concerning power, area, robustness, ease of composition, testability and performance. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

recall What we actually need When can SNK use its input? When it is valid and consistent f(x) SRC SNK When can SRC apply the next input? When SNK has consumed the previous one Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

recall Ideal Design Method An ideal design method … minimizes power consumption miminizes area overhead naturally supports the design process naturally aids verifiability yields robust circuits yields fast circuits. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Outline The Handshake Principle Sutherland‘s Micropipeline Transition Signaling & Muller C-Element The Bounded Delay Approach Other Delay Models Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

recall Our Options We must only use consistent input vectors How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

What do we change? Data flow remains the same; data transfer is the ultimate goal Control flow is different: global clock from syn world replaced by handshake now Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Asynchronous Philosophy
„The control flow requires agreement between source and sink. For this purpose they need to communicate“ Source indicates capture condition for sink. Sink indicates issue condition for source. „HANDSHAKE“ Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Handshake Principle REQ: „Data word valid, you can use it“ When can SNK use its input? When it is valid and consistent f(x) SRC SNK When can SRC apply the next input? When SNK has consumed the previous one ACK: „Data word consumed, send the next“ Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Real-life comparison Synchronous systems: train airplane school,… Handshake-like systems: family departure with car discussion catching a fish Why these different schemes? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Micropipeline: Principle
ACKn REQn-1 ACKn+1 C C REQn f(x) R1 R2 Tclk so bemessen, dass F(x) einschwingen können und sicher den Wert angenommen haben. capture „bundled data“ (handshake performed for „bundle“ of data) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

A very Important Detail
The handshake establishes a closed-loop control for the data flow between sender and receiver This makes operation more robust than in the synchronous (= open-loop) case The art of asynchronous design is to make many of these closed loops interoperate properly This is much more complicated than a synchronous design. Time is continuous now, no more discrete Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Micropipe: Capturing capture data if predecessor has new data available (REQn-1) and successor is ready to accept new data (ACKn+1) produce  at capture (output) after  of REQ and  of ACK Muller C-Element REQn-1 ACKn+1 C Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

recall Muller C-Element IF a = = b THEN y = a ELSE hold y a b C y reset a a C RS y y b b set Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Muller C-Element: Circuit
[Martin] [Sutherland] [van Berkel] Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline „FIFO for transitions“ C RIN AOUT ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline initial state C C RIN AOUT C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline request (rising edge) C C RIN AOUT C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline request passes stage 1 C C RIN AOUT C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline request passes stage 2 C C RIN AOUT C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline request passes stage 3 => output C C RIN AOUT C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline further request (falling edge) C C RIN AOUT C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline new request passes stage 1 C C RIN AOUT C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline new request passes stage 2 C C RIN AOUT C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline new request blocked for stage 3 C C RIN AOUT Req 1 remains „stored“ C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline one more request … C C RIN AOUT C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline … passes stage 1 only … C C RIN AOUT C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline ... ands remains stored there C C RIN AOUT Req 3 stored here Req 2 stored here Req 1 stored here C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline acknowledge from output (rising edge) C C RIN AOUT Req 3 Req 2 Req 1 C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline ack passes stage 3 C C RIN AOUT C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline stage 2 is now free for… C C RIN AOUT Req 3 Req 2 C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline … request from stage 1 C C RIN AOUT Req 3 Req 2 C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline new ack (falling edge) … C C RIN AOUT Req 3 Req 2 C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline ... allows remaining request to move up to stage 3 C C RIN AOUT Req 3 C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Elastic Pipeline ready for new req or ack C C RIN AOUT Req 3 C ROUT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Micropipe: Implementation
Capture/Pass Register ACK comb comb comb REQ Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Capture/Pass Register
must react to both edges („two phase handshake“) has dedicated input for both, „capture“ and „pass“ has delayed output for both control inputs („capture done“, „pass done“) to make sure capture occurs before „capture done“ is output c pD cD p Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Transition Signaling Information conveyed by edges, not by state 1 1 1 A0 A1 Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

recall Terminology consistent DW: all bits belong to the same context valid signal: result of function applied to consistent DW Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Trans. Signaling - Example
B=1 B0 B=0 B1 Y = A or B Y0 Y=1 Y1 Y=1 Lecture "Advanced Digital Design" A © A. Steininger & M. Delvai / TU Vienna

Closed loop vs. open loop
Previous example assumed a certain procedure: one input changes (once!) other input changes (once!) then output changes (once!) Is this realistic? NO, if inputs are not correlated with output („open loop operation“) YES, in case of synchronization by means of handshake, i.e. in Micropipeline („closed loop operation“) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

2 Phase vs. 4 Phase 2 phase protocol (transition signaling): 4 phase protocol (level signaling) REQ REQ ACK ACK REQ REQ ACK ACK Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Push vs. Pull Channel Push channel: sender faster than receiver sender provides data with REQ; waits for receiver‘s ACK for these; Pull channel: receiver faster than sender receiver requests next data (REQ); sender provides these plus ACK Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Micropipe: Implementation
comb comb comb DELAY ELEMENT Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The need for a delay REQ: „Data word valid, you can use it“ event = issue of data word ! race condition ! f(x) SRC SNK ACK: „Data word consumed, send the next“ event = latching of data word safe (?) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Example: Centronix Data „REQ“ „ACK“ [Centronix Spec for ETRAX100LX, „Fastbyte Mode“] Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Criticality of ACK f(x) FF2 SRC SNK „latch!“ cannot measure „act of latching“ as an event use latching command instead fork produces race between trigger process and next data wave race is uncritical (but still exists!) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Bounded Delay approach
TRGSNK (REQ) tSRC tSNK Timer SRC Timer SNK TRGSRC (ACK) coordinate SNK & SRC by a handshake This works (quite) well for „ACK“, but still requires a timer-solution for REQ So what have we actually gained? Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

recall The Issue Condition tSNK Control TRGSRC: Have SRC issue the next data word such that the current one can still be safely consumed by SNK. Formal Condition: tinvalid,x > tsafe,x msrc > - Dinvalid Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Bundled Data: Issue Cond.
Delay source trigger by tsnk = Dsnktrg + Dcons+ msrc This is the delay between „capture“ and „capture done“ in the micropipeline. For tsnk = 0 we end up like in the synchronous case: msrc = -(Dsnktrg + Dcons) this is not safe, but works, as long as Dinvalid > Dsnktrg + Dcons Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Criticality of REQ f(x) SRC SNK cannot use issue trigger as an event: produces unacceptable race between data and REQ must introduce timer (bounded delay) Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

recall The Capture Condition tSRC Control TRGSNK: Have SNK capture data only after it has become consistent. Formal Condition: tcons,x > tsnkrdy,x msnk > - Dsnktrg Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Bundled Data: Capture Cond.
Delay source trigger by tsrc = Dsrc + Dproc + Dsnk + msnk This definitely requires a delay element. Like in the synchronous case we end up estimating the involved delays Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Softening the restrictions
synchronous model known bounds for delays, global timing bounded delay model (fundamental) known bounds for absolute delays, local timing scalable-delay-insensitive model bounds for relative deviation between delays known quasi-delay-insensitive output paths of a fork have same delay delay insensitive no restrictions on delays (just finite) syn: optimistisch, immer schwieriger zu erfüllen Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

The limits of true DI generalized structure of asyn circuit: A‘s logic A X G shared logic B B‘s logic single-output gate G with at least 2 inputs (A, B) need feedback for all inputs => FORK (control loop) if G fires upon receipt of 1st feedback (say A) => other path (B) gets out of sync => hazard => G needs to wait for transitions on all its inputs => can only use Muller C-gate, but not AND, OR, … Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Drawback of the delay the skew problem still exists (!) need to determine suitable value for D need to make worst case assumptions for determination of D does not work without constraints on the individual path delays „Bounded Delay Model“ Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

recall Criticality of REQ f(x) SRC SNK cannot use issue trigger as an event: produces unacceptable race between data and REQ must introduce timer (bounded delay) OR: find better event (downstream) completion detection Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Current Sensing: Idea Transitions on data rails cause dynamic current In the absence of dynamic current data must be stable current sensor can be used for completion detection Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Current Sensing: Problems
inversion of causality is not safe: What if bit changes after circuit has been considered stable? What if no bit changes? same data word transmitted again leakage dominates – proportion of dynamic current is decreasing current sensor is undesired analog circuitry Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Gain of Bounded Delay timer settings need to determine clock period circuit functionality is technology dependent considerable design efforts, large design loops need to make worst-case assumptions necessarily pessimistic no robustness wrt. exceeding them need to maintain global synchrony clock distribution problems power consumption problems  Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Bundled Data at a Glance
single-rail data coding 4- or 2-phase handshake Source: [Sparso 06] Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Conclusion Alternatively to a global time base a handshake can establish the required synchronization between source and sink: The source issues a REQ to signal that new data are valid, and the sink issues ACK when it is ready for the next data. In principle the handshake can establish a closed control loop for data flow, which yields higher robustness but variable timing. The micropipeline is the basic approach for structuring asynchronous circuits. It couples individual source/sink pairs Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

Conclusion The bundled data approach utilizes coupled timers for the control of REQ and ACK. This saves the need for a clock tree, but does not solve the conceptual problem of coupling validity to time. Huffman circuits are useful for designing small sub-circuits and state machines in a glitch-free manner. They do, however not provide a generally applicable design solution. Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna

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