1. 1 Computer Architecture & Assembly Language Spring 2009 Dr. Richard Spillman Lecture 11 – ALU Design

2. 2 Outline Introduction to the ALU Addition Subtraction It’s too much my circuits hurt

3. 3 Introduction to ALU The ALU performs all the data manipulations adding subtracting shifting comparing... It requires a hardware device that accepts multiple data words and a set of commands as input and produces a data word and flag signals as output ALU

4. 4 Possible ALU Structure A high level architecture for an ALU looks like: AB Arithmetic Logic Shift MUX C CC Control command TOPICS: VHDL Arithmetic Logic Shift ALU

5. 5 VHDL Implementation A structural implementation would require a schematic and a data flow implementation would require a set of equations A behavioral implementation would only require the specifications ALU 8 bit data - A, B, C A subset of the possible ALU operations - add, and, xor, shift left, shift right, transfer, increment, decrement

6. 6 ALU Specifications These are the operations of the ALU: ALU S2 S1 S0 Operation 0 0 0 C = Atransfer A to C 0 0 1 C = A + 1increment A 0 1 0 C = A + B add 0 1 1 C = A - 1 decrement A 1 0 0 C = A and B AND 1 0 1 C = A xor B XOR 1 1 0 C = A sr1 shift right by 1 1 1 1 C = A sl1 shift left by 1 ALU A B S C CC

7. 7 ALU Entity The entity is a list of the inputs and outputs ALU Entity alu1 is port ( A, B : in std_logic_vector (7 downto 0); S : in std_logic_vector(2 downto 0); C : out std_logic_vector(7 downto 0); CC : out std_logic_vector(3 downto 0)); end alu1; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; To perform arithmetic operations: ALU A B S C CC

8. 8 ALU Architecture One approach to a behavioral model is to use a case statement in a process block ALU A A L L S S.. M M M M C architecture behav of ALU1 is ALU: process (S,A,B) variable Ao : unsigned(7 downto 0); variable Lo, So : std_logic_vector (7 downto 0); begin ALU AB S For arithmetic operations A A.. Ar: case S(2 downto 0) is when “000” => Ao := unsigned(A); when “001” => Ao := unsigned(A) + 1; when “010” => Ao := unsigned(A) + unsigned(B); when “011” => Ao := unsigned(A) - 1; when others => Ao := (others => ‘X’); end case Ar;

9. 9 Architecture (continued) ALU AB S A A.. L L S S Sr: case S(2 downto 0) is when “110” => So := ‘0’ & A(7 downto 1); when “111” => So := A(6 downto 0) &’0’; when others => So := (others =>‘X’); end case Sr; MUXr: if (S(2) = ‘0’) then C <= conv_std_logic_vector(Ao(7 downto 0),8) ; else if (S(1) = ‘0’) then C <= Lo; else C <= So; end if; end if MUXr; end process ALU; end architecture behav; M M M M C Lr: case S(2 downto 0) is when “100” => Lo := A and B; when “101” => Lo := A xor B; when others => Lo := (others =>‘X’); end case Lr; Variable assignment Built in function

10. 10 ALU Run Enter the code in a VHDL complier (take CC out of the entity), compile, and simulate: ALU Sum of 12 + 2 (hex) ADD Command Code

11. 11 Hardware ALU Look at the individual operations Addition Subtraction Multiplication Division Logic/Shift Operations Implement each in hardware and MUX the outputs ALU

12. 12 Binary Addition The ALU adds binary numbers bit by bit: ALU addition X 1 0 1 1 Y 1 1 0 1 Hence, a hardware adder must have 3 inputs and 2 outputs: Single Bit Adder xixi yiyi cici sisi c i+1 Carry 1 1 1 Sum 1 1 0 0 0

13. 13 4-Bit Adder A four bit adder can be constructed from four single bit adders: ALU addition Single Bit Adder x4x4 y4y4 s4s4 Single Bit Adder x3x3 y3y3 s3s3 Single Bit Adder x2x2 y2y2 s2s2 c0c0 Single Bit Adder x1x1 y1y1 s1s1 c4c4 Start with 4 single bit adders Then ripple the carry lines down the structure

14. 14 VHDL Implementation PROCESS PROCESS: Define the full adder as a component and connect four of the components in the architecture ALU addition Entity library ieee; use ieee.std_logic_1164.all; entity four_add is port ( A, B: in std_logic_vector (3 downto 0); Cin : in std_logic; S : out std_logic_vector (3 downto 0); Cout : out std_logic); end four_add;

15. 15 Architecture ALU addition architecture struc of four_add is component full_add port (A, B, Cin : in std_logic; S, Cout : out std_logic); end component; signal C1, C2, C3 : std_logic; begin g1: full_add port map (A(0), B(0), Cin, S(0), C1); g2: full_add port map (A(1), B(1), C1, S(1), C2); g3: full_add port map (A(2), B(2), C2, S(2),C3); g4: full_add port map (A(3), B(3), C3, S(3), Cout); end struc;

16. 16 Speed One problem with our 4-bit adder is that it is slow: ALU addition Single Bit Adder x4x4 y4y4 s4s4 Single Bit Adder x3x3 y3y3 s3s3 Single Bit Adder x2x2 y2y2 s2s2 c0c0 Single Bit Adder x1x1 y1y1 s1s1 c4c4 20 nsec Time 0 20 nsec 40 nsec 60 nsec 80 nsec Carry Lookahead or redundant hardware adders are used to provide faster addition

17. 17 Extended Addition Question: Early microcomputers were only 8 bit machines. How could you add 16 or 32 bit integers? On 16 bit machines how do you add 32 bit integers? Intel solution: ADC dest, source Usage rules are the same as for ADD dest = dest + source + carry flag Example AX = 1000h, BX = 20, CF = 1 ADC AX, BX ; ALU addition

18. 18 Subtraction There are three methods of signed addition based on the representation of negative numbers ALU addition subtraction Sign-Magnitude One’s Complement Two’s Complement

19. 19 Sign-Magnitude Representation: the MSB is a sign bit (0 for +, 1 for -) Example: 0 0 0 0 0 1 0 1 is +5 and 1 0 0 0 0 0 1 1 is -3 Addition Rule: If the sign bits are the same, add the magnitudes. If the sign bits are different, subtract the smaller magnitude from the larger and determine the new sign bit ALU addition subtraction

20. 20 One’s Complement Representation: negative numbers are formed by complementing each bit of the positive sign-magnitude representation Example: 0 0 0 0 0 1 1 0 is + 6 and 1 1 1 1 1 1 0 0 is - 3 Addition Rule: (see next slide) ALU addition subtraction

21. 21 1’s Complement Subtraction RULE: add bit by bit add the high order carry to the result EXAMPLEs ALU addition subtraction +3 0 0 0 0 0 0 1 1 +6 0 0 0 0 0 1 1 0 +9 0 0 0 0 1 0 0 1 -3 1 1 1 1 1 1 0 0 +6 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 Add the carry 1

22. 22 Two’s Complement Representation: negative numbers are formed by complementing every bit and adding 1 EXAMPLE: 0 0 0 0 1 0 0 0 is +8 and 1 1 1 1 1 0 0 0 is -8 Addition Rule: add bit by bit ALU addition subtraction

23. 23 Example Two’s Complement Addition ALU addition subtraction +8 0 0 0 0 1 0 0 0 -2 1 1 1 1 1 1 1 0 +6 0 0 0 0 0 1 1 0 (ignore the carry) -12 1 1 1 1 0 1 0 0 -15 1 1 1 1 0 0 0 1 -27 1 1 1 0 0 1 0 1 Overflow Overflow: if the signs are different ignore the carry out but if the signs are the same and the result has a different sign then an overflow condition exists

24. 24 Extended Subtraction SBB - subtract with borrow SBB destination, source destination = destination - source – CF Usage: just like ADC AX = 1000h, BX = 20, CF = 1 SBB AX, BX ; ALU addition subtraction