1. Computer Arithmetic

2. Integer Representation Sign-magnitude representation +5 -5 2’s complement representation +5 -5 magnitudes 000001010 1 11111011

3. Addition / Subtraction Hardware M=0 addition A ← A + B M=1 subtraction A ← A + B +1 A register Enable Carry-in complementer Adder B register M C Carry-out V

4. Addition / Subtraction Algorithm 2’s complement Overflow V=1 if XOR of the last two carries is 1 V=0 otherwise AdditionSubtraction A ← A + B V←overflow A ← A + B + 1 V←overflow A register Enable Carry-in complementer Adder B register M C Carry-out V

5. Addition / Subtraction Algorithm Sign-magnitude AdditionSubtraction as AsBsAsBs AsBsAsBs CA ← A+ B +1 V ← 0 CA ← A+B V ← C as C A ← A+1 A s ← A s A s ← 0 as A =1=0=1 =0 A s =B s A<BA≥B =0≠0 =0=1 A s =B s A s ≠B s

6. Addition / Subtraction Algorithm Sign-magnitude AdditionSubtraction as AsBsAsBs AsBsAsBs CA ← A+B+1 V ← 0 CA ← A+B V ← C as C A ← A+1 A s ← A s A s ← 0 as A =1=0=1 =0 A s =B s A<BA≥B =0≠0 =0=1 A s =B s A s ≠B s Ex: (+3)+(+5) A s =0 A=0011 B s =0 B=0101 A s  B s =0A+B=1000 C=0 V=0 Result: A s =0A=1000 Ex: (-3) − (+5) A s =1 A=0011 B s =0 B=0101 A s  B s =1A+B=1000 C=0 V=0 Result: A s =1A=1000

7. Addition / Subtraction Algorithm Sign-magnitude AdditionSubtraction as AsBsAsBs AsBsAsBs CA ← A+B+1 V ← 0 CA ← A+B V ← C as C A ← A+1 A s ← A s A s ← 0 as A =1=0=1 =0 A s =B s A<BA≥B =0≠0 =0 =1 A s =B s A s ≠B s Ex: (+5) + (-3) A s =0 A=0101 B s =1 B=0011B+1=1101 A s  B s =1A+B+1=0010 C=1 V=0 Result: A s =0A=0010 Ex: (-3) − (-5) A s =1 A=0011 B s =1 B=0101B+1=1011 A s  B s =1A+B+1=1110 C=0 V=0 1110+1=0010 Result: A s =0A=0010

8. Multiplication Hardware A register Adder Q registerC B register Q0Q0 Q -1

9. Multiplication Algorithm Sign-magnitude Ex: 3 * 5 M s =0 M=0011 (multiplicand) Q s =0 Q=0101(multiplier) Result: A s =0 (M s  Q s ) AQ=00001111 CAQ 000000101 A ← A+M00011 Shift right000011010 Shift right000001101 A ← A+M00011 Shift right000011110 Shift right000001111

10. Multiplication Algorithm 2’s complement (Booth’s Alg.) Ex: (-3) * 5 M=1101 (multiplicand) M+1=0011 Q=0101 (multiplier) Result: AQ=11110001= -15 AQQ -1 000001010 A ← A - M0011 Arith. Shift right000110101 A ← A + M1110 Arith. Shift right111101010 A ← A - M0010 Arith. Shift right000100101 A ← A + M1110 Arith. Shift right11110001

11. Division Hardware A register Adder Q registerC B register Q0Q0

12. Division Algorithm Sign-magnitude Ex: 14  5 M s =0 M=5=0101 (divisor) M+1=1011 Q s =0 Q=14=1110 (dividend) Result: A s =0 (M s  Q s ) Q=0010 (quotient) A=0100 (remainder) AQ 00001110 Shift left00011100 A ← A - M1100 A<0 A ← A + M0001 Shift left00111000 A ← A - M11101000A<0 A ← A + M0011 Shift left01110000 A ← A - M00100001A>0 Shift left01000010 A ← A - M11110010A<0 A ← A + M0100

13. Floating-point Representation mantissa x radix exponent radix=2 Sign-magnitude 2’s complement representation mantissaexponents (significand)

14. Biased Representation integerno bias2 k-1 (=8)2 k-1 -1 (=7) -810000000 -7100100010000 -6101000100001 -5101100110010 -4110001000011 -3110101010100 -2111001100101 111101110110 0000010000111 1000110011000 2001010101001 3001110111010 4010011001011 5010111011100 6011011101101 7011111111110 81111 mantissa x radix exponent radix=2 Sign-magnitude 2’s complement representation exponent + bias mantissaexponents (significand)

15. IEEE Standard 32-bit Floating-point Representation 1 8 bits 23 bits Bias is 2 k-1 -1= 127 The leftmost 1 in fraction is implied. biased exp. fractions

16. IEEE Standard 32-bit Floating-point Representation 1 8 bits 23 bits Bias is 2 k-1 -1= 127 The leftmost 1 in fraction is implied. biased exp. fractions TypeSign Actual Exponent Exp (biased) Exponent fieldSignificand (fraction field)Value Zero 0−12700000 000 0000 0000 0000 0000 00000.0 Negative zero 1−12700000 000 0000 0000 0000 0000 0000−0.0 One 001270111 1111000 0000 0000 0000 0000 00001.0 Minus One 101270111 1111000 0000 0000 0000 0000 0000−1.0 Smallest normalized number *−12610000 0001000 0000 0000 0000 0000 0000 ±2 −126 ≈ ±1.18×10 −38 Largest normalized number *1272541111 1110111 1111 1111 1111 1111 1111 ±(2−2 −23 ) × 2 127 ≈ ±3.4×10 38 Positive infinity 01282551111 000 0000 0000 0000 0000 0000+∞ Negative infinity 11282551111 000 0000 0000 0000 0000 0000−∞ Not a number *1282551111 non zeroNaN * Sign bit can be either 0 or 1.

17. Floating-point Addition/Subtraction Algorithm Ex: 10.0 + 1.5 using 4-bit registers X = 1010.0 = 0.1010 x 2 4+b Y = 1.1 = 0.11 x 2 1+b = 0.00011 x 2 4+b S significand exponent X Y Z Z= 11.0 10 10104+b0 00014+b0 10114+b0

18. Floating-point Multiplication Algorithm Ex: 10.0 + 1.5 using 4-bit registers X = 1010.0 = 0.1010 x 2 4+b Y = 1.1 = 0.11 x 2 1+b Add exponents and subtract bias: ((4+b) + (1+b)) – b = 5+b Z= 0.01111 x 2 5+b = 0.1111 x 2 4+b

19. Floating-point Division Algorithm Ex: 10.0 + 2.0 using 4-bit registers X = 1010.0 = 0.1010 x 2 4+b Y = 10.0 = 0.10 x 2 2+b Subtract exponents and add bias: ((4+b) - (2+b)) + b = 2+b Z= 0.101 x 2 2+b