1. Trigger System of BES III LIU Zhen’an Inst. of High Energy Physics, Beijing June 5-6 2002

2. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 2 Outline Estimation of event rate Challenges to BESIII trigger Trigger principle Trigger scheme description Present status Summary

3. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 3 Estimation of event rate Purpose of trigger system: to accept all interested events to rejects as much background as possible DAQ is sustainable With good design of MDC,TOF and EMC trigger, we estimate that total trigger rate = good event rate (~2000, L BEPCII = 1  10 33 cm -2 s -1 ) + bhabha rate (~800,to be pre-scaled) + cosmic event rate (<200,from 1500) + beam background rate (<2000,from 13MHz) = ~ 4000 Hz Fig:Backgrounds rate vs beam current At BESII/BEPC

4. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 4 The principle of BESIII trigger No dead time in trigger system Pipeline processing must be used in trigger ( Latch-process-decision mode not possible in 8ns) Latency of trigger signal necessary Challenges to BESIII trigger design High good event High Backgrounds Multi-bunches(93),small bunch spacing(8ns)

5. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 5 The principle of BESIII trigger(2)-data flow Hardware trigger + software filter FEE signal splitted: trigger + FEE pipeline FEE pipeline clock 40MHz Level 1(L1): 3.2  s FEE Control Logic checks L1 with FEE pipeline clock L1 YES: moves pipeline buffer data L1 No : overwritten by new data BESIII FEE pipeline and Data flow Detector switch Level 1 FEE pipeline Readout buffer Farms Disk Time Reference 0 s 3.2  s Ev.Filter PowerPC

6. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 6 Block Diagram of BES III Trigger Global Trigger Logic 3.2  s TOF MDC EMC MU DISC Mu track DISC TrigSum Track Finder Etotal Sum Hit/Seg Count Track Seg. Finder DAQ RF TTC TC Sum L1P CLOCK Track Match Energy Balance Cluster Counting

7. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 7 Nswires 9096 N axial 4096 N stereo 5000 N layers 47 Nlaxial 19 Nlstereo 28 N pivot cells ax 96/120/208/312/336 N pivot cells st 48/72/160/184/236/264/288 N spcells/sector 32/16 MDC Trigger-Signals

8. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 8 MDC trigger scheme (axial+stereo) total 300 FEE cards, 5 crates with PowerPC TSF cards GTSF BLT PTD 9096 2008 300 cards on FEE 16X2 16 36Mod.3crates 16Mod.,1crate Axial& stereo TRK CNT GLT

9. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 9 Private FORTRAN code MDC structure + hits Trigger scheme Tasks: Feasibility of trigger scheme Trigger efficiency study Wire in-efficiency influence study Backgrounds rejecting ability study Production of combination data track-segment/track PTD MDC trigger simulation

10. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 10 TSF(Track Segment Finding) Pivot layer Ideal case: same cells,high Pt Ideal case: same cells,high Pt Real case simulation These data is used for TS finding

11. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 11 GTSF(TSF grouping) and BLT(Binary Link Track) BLT Algorithm 2to1 OUT Mem IN Mem Control Mem DAQ Mem O R g a t e From GTSF To GLT Long track Short track

12. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 12 Long track: Reference layer SL11 SL7,SL4 and SL3 3 / 4 or 4 / 4 Short track: Reference layer SL7 SL4 and SL3 3 / 3 Momentum Discrimination(PTD) SL11 SL7 SL4 SL3

13. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 13 Trigger efficiency study With Weff.=96% and 3 / 4 requirement, 95% trigger effi. Achievable for Pt>150MeV track Configuration: Pt > 120 MeV We=1.0 We=0.95

14. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 14 very good trigger efficiency for single artificial tracks with 3 / 4 very good rejection of artificial cosmic rays 10cm away from vertax Efficiency for physics channel to be done when input from GEANT based MDC simulation is available Rejection for beam backgd to be done when inputs from beam background simulation is avalable MDC background rejection

15. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 15 TOF Trigger 160 Leading Edge Disc Mean Timer Leading Edge Disc Leading Edge Disc Leading Edge Disc Mean Timer L 1i1i &(L 2i-1 or L 2i+1 ) TOF Trigger Master Trigger Timing Hit count and topology logic Discriminator TOFE PMT 88TOFB 88TOFB

16. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 16 EMC trigger Barrel: θ×φ=56×144 = 8064 Endcap: 120 、 120 、 120 、 96 、 96 、 96 、 84 、 84 、 84 =1800 Basic trigger unit( trigger cell): sum of 24 crystals outputs

17. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 17 EMC Simulation <20% difference acceptable Gain adjustment for each crystal+PD+PreAmp chain Trigger Cell should be at least 4X4 =16 crystals. 4X6=24 is taken

18. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 18 BESIII EMC trigger scheme Gain Adj. FEE 8ch sum

19. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 19 Track Matching scheme Total 40VME mod. 2 VME crates,2 PowerPC TOF Track Distribution BEMC Track Distribution EEMC Track Distribution Input Signals Delay Input Signals Delay Input Signals Delay Input Signals Delay Matched Track Count To Main Trigger Controller Barrel Track Match Eadcap Track Match From TOF Trigger From EEMC Trigger From MDC Trigger From BEMC Trigger

20. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 20 Global Trigger (GLT) TOF-T Reset To TRG Sub-system Trigger Conditions L1 Programmable Input Signal Delay Programmable Trigger Event Decision Programmable Pre-scale Trigger Controller Clock Processor RF Multi-Scaler CHK INIT BUSY Trigger EVT E-TYPE Trigger Signals Distribution To Electronics TDC EMC-T EEMC-T Inputs: sub-detector conditions Time adjustment trigger table Pre-scaling of some event types

21. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 21 Timing and handshaking with DAQ CLK L1 Tdead Tlife 3s3s BUSY CHK TRG#=256 500ns GEVT Trigger pipeline clock f RF = 499.8 MHz f f RF /12  40MHz Handshaking with DAQ

22. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 22 Present Status Trigger scheme is drafted Trigger simulation goes well, will go further with help from MC group Development tools ready and working Xilinx Foundation Protel PCB Rom programmer

23. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 23 Present Status(2) Experiment Board for VME Module Design Designed base on FPGA Be used for testing other VME module’s functionality Pipelined digital signal generator Designed on Xilinx Foundation Downloaded on Exp. Board Signal Sequence Programmable Signal length programmable Readback Check TTL/LVDS high reliability

24. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 24 Present Status(3) Clock Divider Experiment VMS BUS extender and signal display Digital programmable signal delay module of 16 channel is under designing. MDC TSF board is modeled in FPGA with 32 inputs, and simulated, continue further User Bus for trigger crate(VME P2) defined(draft)

25. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 25 Summary Hardware trigger + software filter L1 latency: changed to 3.2  s Pipeline clock: 40 MHz Monte Carlo simulation goes well and will continue backgrounds, MDC, EMC trigger schemes Preliminary design drafted Some modules designed Further/detailed designing undergoing Welcome collaboration domestic and abroad

26. Zhen'An LIU, IHEPBESIII Collab. Meet. Jun.5 2002,Beijing 26 THANK YOU ! WELCOME COMMENTS AND SUGGESTIONS END