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1 First large DEPFET pixel modules for the Belle II Pixel Detector Felix Müller Max-Planck-Institut für Physik DPG-Frühjahrstagung der Teilchenphysik,

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Presentation on theme: "1 First large DEPFET pixel modules for the Belle II Pixel Detector Felix Müller Max-Planck-Institut für Physik DPG-Frühjahrstagung der Teilchenphysik,"— Presentation transcript:

1 1 First large DEPFET pixel modules for the Belle II Pixel Detector Felix Müller Max-Planck-Institut für Physik DPG-Frühjahrstagung der Teilchenphysik, T96.1 Hamburg 2016, March 3, 2016

2 2 SuperKEKB upgrade Belle II Nano beam scheme  much smaller beam size (~60 nm) & increased beam currents (x2)  L = 8 x 10 35 cm -2 s -1 (40 times larger than in KEKB)  E e- = 7 (8) GeV & E e+ = 4 (3.5) GeV (  = 0.42 (KEKB)  0.28 (SuperKEKB))  E cm = 10.58 GeV - Y (4S) Nano beam scheme  much smaller beam size (~60 nm) & increased beam currents (x2)  L = 8 x 10 35 cm -2 s -1 (40 times larger than in KEKB)  E e- = 7 (8) GeV & E e+ = 4 (3.5) GeV (  = 0.42 (KEKB)  0.28 (SuperKEKB))  E cm = 10.58 GeV - Y (4S) positron (4 GeV) electron (7 GeV) 5.0 m 7.4 m Changes involving the Vertex Detector (VXD):  Two layers of DEPFET pixel detector (PXD) (at 14 and 22 mm from IP)  Four layers of Double Sided Si-Strip Detector (SVD) with a larger radius Changes involving the Vertex Detector (VXD):  Two layers of DEPFET pixel detector (PXD) (at 14 and 22 mm from IP)  Four layers of Double Sided Si-Strip Detector (SVD) with a larger radius 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016

3 3 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016 DEPFET (DEPleted p-channel Field Effect Transistor) impinging particle Clear Turn on DEPFET source Gate → Low noise → Low power → High signal/noise-ratio → Non-destructive readout → Low noise → Low power → High signal/noise-ratio → Non-destructive readout Produced at Semiconductor Laboratory of the Max-Planck Society

4 4 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016 Control and readout electronics SWITCHER Fast voltage pulses up to 20 V to activate gate rows and to clear the internal gate JTAG for interconnectivity tests 64 output drivers for both gate and clear channels  address 32 matrix segments 768 rows  192 electrical rows  6 ASICs needed per module SWITCHER Fast voltage pulses up to 20 V to activate gate rows and to clear the internal gate JTAG for interconnectivity tests 64 output drivers for both gate and clear channels  address 32 matrix segments 768 rows  192 electrical rows  6 ASICs needed per module Drain Current Digitizer (DCD) Keeps the columns line potential constant 8 bit ADCs Compensates for pedestal current variation (2bit DAC) Programmable gain and BW 256 input channels (4 per module) Drain Current Digitizer (DCD) Keeps the columns line potential constant 8 bit ADCs Compensates for pedestal current variation (2bit DAC) Programmable gain and BW 256 input channels (4 per module) Data Handling Processor (DHP) Pedestal correction Common mode correction Data reduction using the zero suppression Triggered readout scheme introduces further data reduction Controls the Switcher sequence Data Handling Processor (DHP) Pedestal correction Common mode correction Data reduction using the zero suppression Triggered readout scheme introduces further data reduction Controls the Switcher sequence Kapton Flex cable Power Supply via soldered contacts and bond wires Data transmission via bond wires 4 layers, 48 cm Kapton Flex cable Power Supply via soldered contacts and bond wires Data transmission via bond wires 4 layers, 48 cm DEPFET Pixel i,j,v 768x250 pixel x 2

5 5 PXD9 Pilot Run Drain Current Digitizer Data Handling Processor 768 x 250 = 192.000 DEPFETs Switcher Current Capacitors & Resistors SMD 01005, 0201, 0402 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016 Readout Time: Full Speed: ~20µs Reduced Speed: ~24.5µs

6 6 PXD9 – W30-OB1 – Pedestals 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016

7 7 PXD9 – W30-OB1 – Noise µ=0.60 ADUµ=0.63 ADU µ=0.59 ADUµ=0.60 ADU 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016

8 8 PXD9 – W30-OB1 – Laser scan Laser signal ~2-4mip, read out at full speed with a noise of ~1.8 ADU (laser instability and system noise) ~105 ns/row, of which ~26ns are used for clear pulse (8 ticks of 32) 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016

9 9 PXD9 – W30-1 – Clear behavior OB  Consecuitive frames are readout  Timing of the laser set to have one laser pulse within 4 frames  Threshold of zero suppression is set to 5 ADU Laser spot 91ADU 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016

10 10 PXD9 – W30-OB1 – Source Measurement 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016

11 11 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016 Summary and Outlook  To fully exploit the high luminosity (increase by factor 40), the vertex detector of Belle II is currently upgraded -> low material budget pixel detector required  Excellent spatial resolution of ~ 15  m; occupancy ~ 1%, fast readout (50 kHz frame rate), huge number of pixels (~ 8 Mpix) => fits all the requirements for Belle II  Complex DEPFET technology; fully functional; successful demonstration in lab and beam tests  Thinning of sensitive area down to 50µm / 75  m (0.2% X 0 ), minimizing multiple scattering;  Low power consumption ~ 18 W per ladder  ASICs and Sensors close to final version  Signal to Noise: ~ 40 (including noise from ASICs)  Many aspects not covered in this talk; though in development by the Collaboration  First real sensor (W30-OB1) shows a good clear performance over the entire area  W30-OB1 shows spectrum of all 24 DCD/Switcher regions with reduced speed Outlook:  Optimization of ASIC settings & Supply voltages  Test Beam at April 2016 at DESY

12 12 Time dependent measurements of CP violation (Belle: ~200µm) Y(4S) is the first resonance just above the BB production threshold Only BB pairs are produced, and are quasi at rest in the Y(4S) frame 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016

13 13 Vertex Detector (VXD) Tasks of the vertex detector: Reconstruction of primary, secondary, … vertices of short-lived particles decay of particles is typical in the order of 130 µm from the IP (reduced boost) Detect tracks of low momentum particles (in high B field) which cannot make it to the main tracker →Innermost detector system as close as possible to IP (higher background & event rate) →highly granular pixel sensors; provide most accurate 2D position information →should be massless and still provide a large enough S/N →Design and specifications to a larger extent driven by machine/beam characteristics →Beam background, radiation damage, occupancy … 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016

14 14 Radiation Tolerance 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016 Gate Dielectrics: ~ 200nm  Radiation field at Belle II dominated by ~MeV electrons/positrons from QED beam background Ionizing Radiation - Total Ionizing Dose (TID) (~2Mrad/a at Belle II) Positive fixed oxide positive charge  ∆V T interface trap density  reduced mobility (g m ) higher 1/f noise Non Ionizing Energy Loss (NIEL) (10 12 n eq /cm²/year at Belle II) Leakage current increase  shot noise Trapping not considered to be critical Type inversion expected after 10 14 n eq /cm²

15 15 Radiation Tolerance 03.03.2016 Felix Müller, DPG Frühjahrstagung, T96.1, 3.3.2016 R&D since 2008:  Reduce t ox  Optimize gate dielectric layer  Vt(10Mrad): ~15V  3 V The remaining small threshold voltage shift can easily be compensated by a shift of the operating voltages of the DEPFET!  Safe operation for about 10 years in Belle II


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