1. Yield measurements on PXD9-7 after 2nd metal Paola Avella, Daniel Klose, Christian Koffmane, Jelena Ninković, Rainer H. Richter for the MPP/HLL team

2. 12. May 2016D. Klose, MPP & HLL 2 Outline & Motivation 1. Global tests on the modules to get info on: Diode integrity Shorts in the polylines 2. Tests of DEPFET transfer characteristics at the first gate row to get info on: Shorts Opens  map of the fanout with precise localisation of faults  possibility of rework in faulty areas

3. 12. May 2016D. Klose, MPP & HLL 3 Wafer and chip layout The batch of PXD9-7 wafers consists of four wafers: All four wafers (W31, W37, W38 and W40) are currently undergoing further processing IF OF1 OF2 OB1 OB2 IB

4. 12. May 2016D. Klose, MPP & HLL 4 Wafer and chip layout The batch of PXD9-7 wafers consists of four wafers: All four wafers (W31, W37, W38 and W40) are currently undergoing further processing

5. 12. May 2016D. Klose, MPP & HLL 5 Pretests – Clear vs Source PXD 9-7 W31W37W38W40 IF ok OF1 ok badok OF2 okbad ok OB1 ok OB2 ok badok IB ok PXD 9-6 W30W35W36 IF ok OF1 ok OF2 ok OB1 ok bad OB2 okbadok IB okbadok The All Clear and the Source testpad are connected to all pixels over bus structures. All Clear and Source regions tested in reverse bias

6. 12. May 2016D. Klose, MPP & HLL 6 The poly1/poly2 electrical nets

7. 12. May 2016D. Klose, MPP & HLL 7 The poly1/poly2 electrical nets

8. 12. May 2016D. Klose, MPP & HLL 8 The poly1/poly2 electrical nets

9. 12. May 2016D. Klose, MPP & HLL 9 Pretests – Shorts in Polylines PXD 9-7 W31W37W38W40 IF1-22+1-20 OF11-32+ 1 OF21-22+ 1 OB112+ 0 OB2112+0 IB01-3 0 PXD 9-6 W30W35W36 IF22+1-3 OF1011-2 OF211-21 OB1201 OB211-2 IB201 Combined results of the pretests: 1. AllGate vs ClearGate 2. AllGate vs Source 3. ClearGate vs Source

10. 12. May 2016D. Klose, MPP & HLL 10 Wafer and chip layout The batch of PXD9-7 wafers consists of four wafers: All four wafers (W31, W37, W38 and W40) are currently undergoing further processing 1st gaterow

11. 12. May 2016D. Klose, MPP & HLL 11 Fan-out types Configuration #1: SMU2 = All Clear (15V – static voltage 1) SMU3 = All Gates (2V – static voltage 2) SMU4 = Clear Gate (5V – static voltage 3) SMU5 = Source (0V – static voltage 4) Configuration #2: SMU2 = Source (0V – static voltage 1) SMU3 = Clear Gate (5V – static voltage 2) SMU4 = All Gates (2V – static voltage 3) SMU5 = All Clear (15V – static voltage 4) Type A: IF, OB1, OB2 Type B: IB, OF1, OF2 Drain pads Clear Gate Source All Gates All Clear Source Clear Gate All Gates All Clear Static voltage 4 3 2 1 4 3 2 1 + automatic probehead PH510 for the voltage sweep [-3 V to 2 V] at the external gate

12. 12. May 2016D. Klose, MPP & HLL 12 System description Probe card with 134 needles in total, arranged in two rows. 126 needles for the drain lines and 4 needles per row for the static voltages. Probe card is connected via two ribbon cables to a conversion board Conversion board distributes the currents to the SMUs and the voltages to the probe card The 126 drain lines are connected to 7 SMUs  18 drain lines per SMU The 4 static voltages are connected to 1 SMU each 1 SMU is used for the single needle for the gate rows.  12 SMUs in total

13. 12. May 2016D. Klose, MPP & HLL 13 Drain Groups, mapping, probing

14. 12. May 2016D. Klose, MPP & HLL 14 Drain Groups, mapping, probing SMU6 DG 1 4200 SMU7 DG 2 4200 SMU8 DG 3 4200 SMUa1 DG 4 2612 #1 SMUb1 DG5 2612 #1 SMUa2 DG6 2612 #2 SMUb2 DG7 2612 #2 chuck step #8 chuck step #1

15. 12. May 2016D. Klose, MPP & HLL 15 Example of the mapping

16. 12. May 2016D. Klose, MPP & HLL 16 Opens & shorts Opens W31W37W38W40 IF 0000 OF1 0100 OF2 0000 OB1 0010 OB2 0031 Shorts W31W37W38W40 IF 1 + 1 D-S*01 strange0 OF1 01 strange00 OF2 0001 OB1 1 G-D*04 D-S*0 OB2 0000 * D-S: Drain to Source short, affecting one drain line ** G-D: Gate to Drain short, also affecting one drain line

17. 12. May 2016D. Klose, MPP & HLL 17 PXD 9-7 estimated yield - assuming successful repair PXD 9-7 W31W37W38W40 IF98.998.499.0100.0 OF199.098.398.499.5 OF299.098.4 99.5 OB199.498.497.9100.0 OB299.5 98.199.9 IB100.099.0 100.0 PXD 9-6 W30W35W36 IF73.498.499.0 OF1100.098.499.0 OF299.599.099.5 OB197.799.498.4 OB299.597.499.0 IB97.9100.0 99.5 Percent Total number of modules18 Prime grade (>=99%)1055.56 % Second grade422.22 % No use422.22 % Useful sensors1477.78 % Percent Total number of modules24 Prime grade (>=99%)1562.50 % Second grade520.83 % No use416.67 % Useful sensors2083.33 %

18. 12. May 2016D. Klose, MPP & HLL 18 Pedestal – First gaterow

19. 12. May 2016D. Klose, MPP & HLL 19 Pedestal – First gaterow Average pedestal [- µA] W31W37W38W40 IF 110122125 OF1 111126118125 OF2 106120118120 OB1 100115 118 OB2 99117125118 PXD 9-6 W30W35W36 IF 106130122 OF1 106122123 OF2 102114117 OB1 99114111 OB2 104114110

20. 12. May 2016D. Klose, MPP & HLL 20 Pedestal spread – First gaterow ΔI [µA] W31W37W38W40 IF 16272629 OF1 22242321 OF2 21202318 OB1 17221922 OB2 18242221 PXD 9-6 W30W35W36 IF 162726 OF1 222423 OF2 212023 OB1 172219 OB2 182422 Pedestal spread:

21. 12. May 2016D. Klose, MPP & HLL 21 Threshold– First gaterow [V] W31W37W38W40 IF 0.0050.0870.0950.078 OF1 -0.0160.083-0.0120.085 OF2 -0.0780.0420.0050.050 OB1 -0.1270.010-0.015-0.009 OB2 -0.1460.0230.813*0.014 Mean Threshold voltages for the first gate row Spread of up to ±0.3 V for the individual drain line Bad module!

22. 12. May 2016D. Klose, MPP & HLL 22 PXD9-6 W35-OF1 Internal Gate Potential Internal gate potential Internal gate potential of one gate row as a function of the clear voltage for 18 drains. An average over the full gate row (1000 drains) gives: Mean internal gate potential: 3.5 ± 0.5 V

23. 12. May 2016D. Klose, MPP & HLL 23 PXD9-6 W35-OF1 Output Characteristics

24. 12. May 2016D. Klose, MPP & HLL 24 Summary and future plans Introduction of a sense line for all four static voltages Yield of the metal system is equal to the pilot run Measurements of Internal Gate potential and Channel length modulation factor for one module of the pilot run match the simulations Wafers are currently further processed and repaired Further tests on test structures after cutting Thank you for your attention!

25. 12. May 2016D. Klose, MPP & HLL 25 BACKUP SLIDES

26. 12. May 2016D. Klose, MPP & HLL 26 System issues/failures (from last SeeVogh meeting – 31.03.15) 1.Chuck not planar  Bad probing in the right hand side of the fan-out (source in conf #2) – (E/W tilt) Bad contacts (higher contact resistance  smaller I ds ) for higher chuck steps (N/S tilt)  NOW SOLVED: Chuck planarized Use of sense line at source contact (currently possible only for conf #2) 2.Electrical failures (due to contact problem in SMU2 preamp of Keithley 4200)  System freeze Bad characteristics due to wrong applied voltage (AC/conf #1 or S/conf #2 – critical)  Need investigation – currently on hold (temporary solution: SMU2 and SMU3 swapped) 3.Electrical failures (in Keithley 2612)  System freeze  Possibly due to a timeout error in the communication between KITE (Keithley GUI) and the instruments: Software upgrade seems to solve the problem via the introduction of time delays (or settling time) and keeping the SMUs in the ON state for the whole duration of the measurement (under investigation!) 4.Software failures (fully understood)  KITE (DAQ software) crash System freeze if data folder remotely accessed

27. 12. May 2016D. Klose, MPP & HLL 27 Yield considerations of the metal system Rainer’s criteria for yield calculation: 0: no faults 1: pixel or column* (drain line) level faults 2: row level faults 3: high impact faults 4: lethal faults 5: to be clarified * Column level faults in Al2 can be repaired by rework (grade 1  0). Rainer’s Yield Criteria W30W35W36 IF300 OF1000 OF2000 OB1110 OB2151 IB040 Yield (%) W30W35W36 IF75.0100.0 OF1100.0 OF2100.0 OB199.899.4100.0 OB299.699.599.8 IB100.00 Yield calculated taking into account the following equation: With D the total number of drain lines (1000) and D s the number of drain lines involved in the short.

28. 12. May 2016D. Klose, MPP & HLL 28 Switch system

29. 12. May 2016D. Klose, MPP & HLL 29 Threshold calculation according to: Dieter K. Schroder: Semiconductor material and device characterisation. Arizona State University (2006), p.223. Threshold voltage around -0.5V

30. 12. May 2016D. Klose, MPP & HLL 30 Threshold calculation according to: Dieter K. Schroder: Semiconductor material and device characterisation. Arizona State University (2006), p.225. Threshold voltage mostly around +0.08V