1. Very good news for People who know Reed-Muller Logic 1.Quantum XOR 1.Quantum XOR is the most important gate in Quantum Logic 2.Synthesis of Quantum Circuits will require methods that are close to spectral and RM- based. 3.New Logic Synthesis is needed 4.Reed-Muller logic uses AND and EXOR gates and expansions.

2. Types of reversible logic and respective gatesreversible conservative The same number of inputs and outputs Toffoli Kerntopf Fredkin Margolus Feynman inverter Double rail inverter Priese switch Interaction Sasao/Kinoshita gates Bubble memory Some ideas of conservative bubble memory can be reused.

3. Types of reversible logicreversible conservative The same number of inputs and outputs Toffoli Kerntopf Fredkin Margolus Feynman inverter Double rail inverter Priese Interaction Sasao/Kinoshita gates

4. Types of reversible logicreversible conservative The same number of inputs and outputs Toffoli Kerntopf Fredkin Margolus Feynman inverter Double rail inverter Priese Interaction Sasao/Kinoshita gates quantum

5. Types of reversible logicreversible conservative The same number of inputs and outputs Toffoli Kerntopf Fredkin Margolus Feynman inverter Double rail inverter Priese Interaction Sasao/Kinoshita gates optical

6. Most often used quantum/reversible gates So far, most of the published methods synthesize quantum permutative circuits with only these gates: 1.NOT 2.CNOT (Feynman) 3.CCNOT (Toffoli) 4.Controlled SWAP (Fredkin) 5.SWAP

7. A B C D 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 X Y Z V 0 0 1 1 1 0 1 1 0 0 1 0 1 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 0 0 Function F Function F -1 X Y Z V 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 A B C D 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 0 1 0 0 0 Forward Function Inverse Function Several methods exist to calculate inverse from forward function Reversible function. Truth table of a one-to-one mapping

8. Background More on Reversible logic This approach is mostly for quantum logic realization For optical and CMOS realizations the k*k assumption is not necessarily used

9. Notation for Fredkin Gates A 0101 CB PQR A 01 P BC QR A circuit from two multiplexers Its schemata This is a reversible gate, one of many C AC’+B BC’+AC C A B

10. Margolus Gate A 0101 CB PQR A 01 C A B ReversibleConservative 3*3 gate These gates are built only from multiplexers

11. The 3 * 3 Toffoli gate is described by these equations: P = A, Q = B, R = AB  C, Toffoli gate is an example of two-through gates, because two of its inputs are given to the output. Toffoli Gate in another notation PRQ * + ABC For some synthesis methods, these other notations are more convenient

12. * + + AB (b) PQ * + A B C PRQ * + ABC PRQ 0 1 Kerntopf Gate Feynman Toffoli Feynman, Toffoli and Fredkin gates are their own inverses

13. The Kerntopf gate is described by equations: P = 1  A  B  C  AB, Q = 1  AB  B  C  BC, R = 1  A  B  AC. When C=1 then P = A + B, Q = A * B, R =  B, so AND/OR gate is realized on outputs P and Q with C as the controlling input value. When C = 0 then P =  A *  B, Q = A +  B, R = A  B. 18 different cofactors! Kerntopf Gate Toffoli gate is simple. Kerntopf gate is good because it has many subfunctions, but its use is difficult Cofactors of this gate are created by setting all its inputs to constants in all possible gates

14. As we see, the 3*3 Kerntopf gate is not a one-through nor a two-through gate. Despite theoretical advantages of Kerntopf gate over classical Fredkin and Toffoli gates, so far there are no published results on realization of this gate. Kerntopf Gate

15. Logic Synthesis for Reversible Logic

16. Toffoli Fredkin A B C F1 D F2 Feynman How to build garbage-less circuits GARBAGE BIT 1 GARBAGE BIT 2 We can decrease garbage at the cost of delay and number of gates We create inverse circuit and add spies for all outputs 2 outputs 2 garbages width = 4 delay = 4

17. Toffoli Fredki n A B C D Feyn man To ffo li Fred kin A B C D Feyn man copy How to build garbage-less circuits A,B,C,D are original inputs inputs reconstructed This process is informationally reversible It can be in addition thermodynamically reversible F1 from spy F2 from spy 2 outputs no garbage width = 4 delay = 9

18. Observations We reduced garbage at the cost of delay and number of gates We were not able to reduce the width of the scratchpad register The method based on spy signals and mirror circuits is absolutely fundamental to reversible and quantum computing.

19. 1. Minimize the garbage 2. Minimize the width of scratchpad register 3. Minimize the total number of gates 4. Minimize the delay Goals of reversible logic synthesis

20. Multi-purpose Portland Decomposition To distinguish this new general decomposition from the well-known decompositions of Ashenhurst, Curtis or Shannon, we call it the Multi- purpose Portland Decomposition, the MP-decomposition for short. This was the earliest published method for reversible circuit synthesis (2001). Many of its components were later on improved and expanded by various authors.

21. Synthesis from (p)KFDDs Preprocessing KFDD – Kronecker Functional Decision Diagrams pKFDD – Pseudo-Kronecker Functional Decision Diagrams

22. Decision Diagrams 1.BDD – Binary Decision Diagrams. Reduced and Ordered. Use only Shannon Expansion. 2.Functional Decision Diagrams – use only Positive Davio Expansion. Ordered, only one variable in a level. 3.Kronecker Functional Decision Diagrams. Use Positive Davio, Negative Davio and Shannon Expansions. One expansion for every variable. 4.Pseudo-Kronecker Functional Decision Diagrams. Can have a mixture of expansions in every level of the diagram.

23. * + * + * + * + …... cici f1f1 f2f2 f3f3 f4f4 k1k1 k2k2 k3k3 k4k4 k5k5 k6k6 Previous levels next levels Other same level This graph shows how a level of Functional Decision Diagram can be replaced by positive Davio gates Kronecker Functional Decision Diagrams

24. * + * + * + * + …... f1f1 f2f2 f3f3 k1k1 k2k2 k3k3 k4k4 k5k5 k6k6 Previous levels next levels Other same level f4f4 cici Transformation of a level to positive Davio gates

25. Example of converting a decision diagram to reversible circuit

26. Starting from Pseudo-Kronecker Functional Decision Diagram

27. fg pD nD S S S S S d a b c e 1 d d 1 0 1 1 0 0 1 01 1 0 1 0 (a) * + (b) * + d f G1 G2 g G3 e b c 0 0 1 1 a

28. Starting from function-driven Decision Diagram fDD = function-driven Decision Diagram

29. S S S y1y1 y3y3 y2y2 0 1 0 1 1 1 0 0 (b) S S S x4x4 x3x3 x1x1 01 0 1 1 10 S x2x2 SS S 0 1 0 1 1 0 0 0 1 (a) y1 =x2  x3  x1x3 y2 =x3  x1  x1x4 y3 =x1  x4  x3x4 y4 =x4 Converting fDDs to reversible circuits Standard BDD Corresponding fDD of Kerntopf Nonlinear preprocessor

30. y1 =x2  x3  x1x3 y2 =x3  x1  x1x4 y3 =x1  x4  x3x4 y4 =x4 * + * + * + x1x1  x1 x1 x3x3 x2x2 y1y1 y3y3 y2y2  x4 x4 x4x4  x3 x3 G2 + x3x3 1 0 0 1 1 G1 h G3 Reversible circuit corresponding to fDD together with preprocessor

31. Open Problems: Is our set of mapping rules sufficient? –(we have currently about 20 rules, but many more can be created). What is the practically best starting point for large functions? KFDD? PKFDD? fDD? How to transform the diagram or the circuit to improve the cost function? What to do in case of rule conflict? How to create rules to decrease garbage?

32. Use of Reversibility Observation: Every synthesis method can be executed forward and backwards Sometimes solution backwards can be simpler

33. A B C D 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 X Y Z V 0 0 1 1 1 0 1 1 0 0 1 0 1 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 0 0 Function F Function F -1 X Y Z V 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 A B C D 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 0 1 0 0 0 Forward Function Inverse Function Several methods exist to calculate inverse from forward function

34. X Toffoli Fredkin A B C Z Y D V Feynman Toffoli Fredkin A B C Z Y D V Feynman X Circuit for function F Circuit for function F -1 F*F -1 =I

35. Method of realization of F 1.1. Find function inverse F -1 of function F. 2.2. Synthesize F -1 using any method for reversible gates 3.3. Draw the schematics of F -1 from gates. 4.4. In the schematics replace every gate by its reverse and change the direction of signals. 5.5. The new schematics is the realization of F.

36. Fredkin A B C =Z  V  Y  Z Z Y D V Feynman X X=G1 Feynman G2=Z  V 0 X YZYZ YZYZ Y+  Z ZVZV YZYZ ZZ 0 Y Y Y Fan-out gate We were not able to find the best realization of F -1 shown earlier Another realization of F -1

37. Compositions and Decompositions

38. Composition Methods Composition methods with matching-based cell selection and complexity measures have been presented by: –Dietmeyer –Schneider –Wojcik –Michalski –Jozwiak, Chojnacki and Volf –DeMicheli library matching –Kravets and Sakallah

39. Uses library of 1*1,2*2 and 3*3 cells For every 3*3 function, a ready solution cascade is stored - see the results of Kerntopf and Storme-DeVos For every reversible gate, all cofactors can be stored (constants and garbage) and used in NPN matching. Gates with more cofactors (like Kerntopf) are better

40. Can be applied to both classical reversible and quantum logic All intermediate functions calculated in terms of input variables Uses equivalence mapping transformations based on NPN-equivalence Synthesis from inputs to outputs and from outputs to inputs, backtracking and look-ahead strategies

41. How to select the cell, its alignment and constants? 1.Select the gate that provides smallest complexity evaluation of the remaining functions and intermediate functions. 2.This works for both forward and backward transformations 3.I propose PPRM for matching because it is easy to implement. Other representations and measures can be used for matching - De Micheli, Dietmeyer, Jozwiak. 4.PPRM – Positive Polarity Reed-Muller Expansion. –Review it if necessary.

42. 0 0 1 1 a + + a c b x y b c  ab c   ab a a Second stage Second stage of decomposition: Fredkin gate First stage First stage of decomposition: Feynman gate Decompositional synthesis of Toffoli Gate from Fredkin and Feynman Gates s t Third stage Third stage of decomposition: Feynman gate Using PPRM representation allows for NPN matching and good evaluation of remaining function complexity

43. 0 0 1 1 a + + a c b x y b c  ab c   ab a a Second stage Second stage of composition: Reversible Expansion for Fredkin gate Third stage Third stage of composition: Feynman gate Compositional synthesis of Toffoli Gate from Fredkin and Feynman Gates s t First stage First stage of composition: Feynman gate NPN matching takes care of permutations and inverters

44. Composition From inputs to outputs What to do if the initial function is not reversible?

45. EXAMPLE Design of a Half- Adder using reversible gates

46. A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 X Y Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 h=A  B g=A*B G 0 0 - 1 0 - 0 1 - Toffoli Z=A*B Restrict to C=0 1. Toffoli gate assumed. 2. New functions X,Y,Z created. 3. C=0 restriction taken 4. Functions h and g of X,Y,Z are createdComposition

47. Toffoli Feynman A B C X=A Y=B =0 Z=AB G =X=A g=Z=AB h=X  Y=A  B Created first Calculated in terms of new variables X,Y,Z and selected Feynman gate Compositional synthesis of non-reversible function of half-adder

48. Adder is composed from half-adders 2 garbage bits and one constant

49. Toffoli Feynman A B C X=A Y=B =0 Z=AB G =X=A g=Z=AB h=X  Y=A  B Another variant assumes Kerntopf gate

50. Heuristics for finding simplest reversible function during composition CCN CN A B 0 A A  B (Sum) A and B (Carry) Toffoli Feynman A B AB  0 AB 00 10 01 10 Mapping of a half-adder 00 01 11 10 This is what we would like to have But this is not reversible, A B A  B A * B

51. CCN CN A B 0 A A  B (Sum) A and B (Carry) Toffoli Feynman A B AB  0 Mapping of a half-adder AB 00 10 01 10 00 01 11 10 A B A  B A * B The simplest way to separate them is to add variable A Heuristics for finding simplest reversible function during composition

52. CCN CN A B 0 A A  B (Sum) A and B (Carry) Toffoli Feynman A B AB  0 AB 000 010 101 110 Mapping of a half-adder 00 01 11 10 This is what we would like to have But this is not reversible, because more outputs than inputs A * B A B A  B A Heuristics for finding simplest reversible function during composition

53. CCN CN A B 0 A A  B (Sum) A and B (Carry) Toffoli Feynman A B AB  0 AB C 001 011 100 111 000 010 101 110 Mapping of a half-adder Positive Davio Gate Now function is reversible of A,B,C arguments. But we still need to decompose it to known gates A * B  C A B C A  B A Heuristics for finding simplest reversible function during composition

54. Search is defined by: –selecting function to be realized –selecting a gate type –selecting its forward or backwards matching –selecting other signals to match –selecting constant Garbage functions are becoming less and less undefined in the process of decomposition They can be used for synthesis We adopt classical AI search algorithms (depth-first, breadth-first, A*,best bound, etc) Search

55. Search cannot be avoided Trade-off between quality of solution and search time The only real improvement is possible through better selection heuristics and better implementation of cell library. Search

56. Using Backward and Forward Search to synthesize from reversible gates 1.Apply gates from inputs 2.Apply gates from outputs 3.Calculate reminder functions 4.Try to reuse signals 5.Add SWAP and COPY (CNOT) gates, if necessary.

57. b 0101 a  c Q g1 = a  b + b  c a R P 0101 1  c G2 =  b +  c + start forwardbackward H=  c+b forward + G3 *  c G4 Library matching cooperation of various methods Illustration of cooperation of various methods to design the Kerntopf gate from Fredkin, Toffoli, Feynman gates and inverters. One fan-out gate for input a, inverter for c and two fan-out gates for  c are not shown.

58. Adaptations of functional decomposition methods

59. G H... G H G H Ashenhurst-like parallel serial New Curtis Curtis-like

60. During graph coloring of an incompatibility graph for nodes with minterms of bound set, two conditions are satisfied: there must be 4 colors every color must be used exactly 2 times. G H... We sacrifice this wire for garbage These two signals should be encoded using 4 symbols Bound set Curtis Decomposition

61. Probability of finding such coloring is increased by having more don’t cares More don’t cares are created by repeating variables in bound and free sets. This principle is the base of all decompositions of reversible functions and relations. Curtis Decomposition

62. Levelized Structures

63. Two-Dimensional Lattice Diagrams for reversible logic

64. Three Types of General Expansions f 01 A f0f0 f1f1 f and A f 0 and f 1 Forward Shannon

65. Three Types of General Expansions g,h and A g 1 A+h 0 A’ 10 1 0 g1g1 h A g 1 A+h 0 A’ Reverse Shannon (b) hoho g

66. Three Types of General Expansions g 1 A+h 0 A’ A g h 10 g 0 A’+h 1 A g, h, and A g 0 A’+h 1 A and g 1 A+h 0 A’ Reversible Shannon

67. 01 1010 - - 0 1 1 1 1001 f garbage g 1010 Z fg X garbage gf h i Y 1 garbage hfgfgh YZ X - - X YZ X 11 1 1 00 0 1 X 00 01 11 10 0101

68. - - 0 1 1 1 - - 1 0 - - X Y Z 1 0 0 1 1 1 - - X - - 1 1 - - - - 1 0 - - 1 - - - - 1 - - - 0 - - 0 - - - = 1 1 0 - - - - - - - - 0 1 - - =1=0=1=0 - - 1 - - - - - - 0 - - YZ This method is fully algorithmic Variable order selection problem Expansion type selection problem

69. Applications of levelized expansion method This method can be used to create arbitrary circuits, not only lattices Any constraint on layout size or shape can be imposed. last-resort approachThe expansion method can be used as the last-resort approach when other methods cannot find solution, in order to reduce the number of variables It introduces garbage and constants, but this is unavoidable when functions are not balanced When realizing multi-output functions start from those that are balanced or closest to balanced.

70. Conclusions New concepts: –(1) Reversible Shannon Expansion for k*k binary Fredkin Gates (k>2) and generalizations - reversible decision diagrams, –(2) Reversible Fredkin Lattice structures for logic based on binary Fredkin gates, –(3) Generalized Composition-Decomposition Methods –(4) Adaptations of Ashenhurst/Curtis decompositions. –(5) Levelized expansions for Shannon and Davio-like gates. –(6) adaptation of BDD-based, decomposition-based and technology mapping methods from standard binary logic

71. Forthcoming Projects and Papers (1) Multiple-valued reversible gates (2) Multiple-valued quantum logic and synthesis methods (3) Fuzzy reversible logic and synthesis methods (4) Ashenhurst/Curtis-like decompositions of multi-valued reversible logic (5) Levelized expansions for multi-valued Shannon and Davio-like gates. (6) Decision Diagrams for binary and MV reversible logic (7) Genetic Algorithm combined with search for quantum logic (8) Regular structures for MV unate, symmetric, threshold and other functions (9) Visual Software

72. What you have to remember? 1.Positive Polarity Reed Muller expansions. 2.Functional Decision Diagrams. 3.Kronecker Functional Decision Diagrams. 4.How to transform diagrams to circuits. 5.Decomposition to gates and sub-circuits that use ancilla bits. 6.Use of spy circuits and mirror circuits. 7.Synthesis from inputs to outputs 8.Synthesis from outputs to inputs 9.Bi-directional synthesis. 10.Levelized Circuits with Davio (Toffoli) and Fredkin gates.