1. 1 Advanced Digital Design Asynchronous Design Automation by A. Steininger and J. Lechner Vienna University of Technology

2. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 2 Design Flow Types 1. Standard HDLs Synchronous-Asynchronous Direct Translation (SADT) Synchronous-Asynchronous Direct Translation (SADT) E.g., Phased Logic, De-synchronization E.g., Phased Logic, De-synchronization 2. Extended Standard HDLs E.g., NCL design flow E.g., NCL design flow 3. Specialized HDLs Petri-nets, STGs, etc. Petri-nets, STGs, etc. Balsa, CHP, etc. Balsa, CHP, etc.

3. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 3 Synchronous-Asynchronous Direct Translation (SADT) Starting point: synchronous circuit description in a standard HDL Starting point: synchronous circuit description in a standard HDL Synthesis with conventional tools into sync. gate-level netlist Synthesis with conventional tools into sync. gate-level netlist Transformation of synchronous netlist into asynchronous netlist Transformation of synchronous netlist into asynchronous netlist Technology mapping Technology mapping Place and Route Place and Route Timing Verification Timing Verification

4. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 4De-synchronization SADT approach SADT approach Design style: Bundled data Design style: Bundled data Substitution of flip-flops by latches Substitution of flip-flops by latches Substitution of clock by local synchronous controllers Substitution of clock by local synchronous controllers De-synchronized circuits... De-synchronized circuits... never halt (liveness) never halt (liveness) perform same computations as synchronous circuit (flow-equivalence) perform same computations as synchronous circuit (flow-equivalence)

5. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 5 De-synchronization Conversion steps 1. Conversion of Flip-flops to latches D-FF separated into master/slave latches D-FF separated into master/slave latches 2. Generation of delays elements for request signals matched to length of critical path of combinational logic matched to length of critical path of combinational logic 3. Implementation and wiring of asynchronous latch controllers

6. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 6 De-synchronization Circuit Architecture [Cortadella et al., 06] De-synchronized circuit Synchronous circuit

7. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 7 De-synchronization Asynchronous Controllers Controller for master/slave latches Controller for master/slave latches 4-phase protocol 4-phase protocol Different controller implementations with more or less concurrency possible Different controller implementations with more or less concurrency possible Non-overlapping Non-overlapping Semi-decoupled 4-phase Semi-decoupled 4-phase Fully-decoupled 4-phase Fully-decoupled 4-phase De-synchronization control De-synchronization control More concurrency => fast pipeline More concurrency => fast pipeline More concurrency => larger controllers More concurrency => larger controllers

8. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 8 De-synchronization Flow Equivalence Definition: Two circuits are flow- equivalent if they... Definition: Two circuits are flow- equivalent if they... have the same set of latches have the same set of latches For each latch, the sequence of stored values is the same in both circuits For each latch, the sequence of stored values is the same in both circuits [Cortadella et al., 06]

9. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 9 De-synchronization Pros/Cons Advantages Advantages Use of standard HDLs Use of standard HDLs Use of industrial-strength synthesis tools Use of industrial-strength synthesis tools Almost no re-education for hardware designers necessary Almost no re-education for hardware designers necessary Simple porting of legacy designs Simple porting of legacy designs Negligible area overhead compared to synchronous implementation Negligible area overhead compared to synchronous implementation Disadvantages Disadvantages 1-to-1 mapping of sync. circuits can lead to sub-optimal designs 1-to-1 mapping of sync. circuits can lead to sub-optimal designs

10. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 10 Null Convention Logic by Theseus Logic Inc. by Theseus Logic Inc. Control based on micropipelines Control based on micropipelines Data path using QDI gates Data path using QDI gates 4-phase dual-rail 4-phase dual-rail Properties Properties Very robust (works for a broad range of operating conditions) Very robust (works for a broad range of operating conditions) High area overhead compared to synchronous implementation: 3-4x High area overhead compared to synchronous implementation: 3-4x

11. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 11 Null Convention Logic Architecture Overview Clear separation of sequential and combinational parts Clear separation of sequential and combinational parts Comparable to synchronous circuits Comparable to synchronous circuits [Kondratyev and Lwin, 02]

12. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 12 Null Convention Logic Design Flow [Ligthart et al., 2000]

13. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 13 Null Convention Logic Design Entry Circuit description in VHDL/Verilog with special coding style Circuit description in VHDL/Verilog with special coding style Explicit coding of register components/control network Explicit coding of register components/control network Data path can be described like for ordinary synchronous circuits Data path can be described like for ordinary synchronous circuits NCL library NCL library Single-rail data signals with data types for multi-valued logic: 0, 1, N, U, X, Z, - Single-rail data signals with data types for multi-valued logic: 0, 1, N, U, X, Z, - Overloaded operators Overloaded operators Hysteresis function for simulation Hysteresis function for simulation

14. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 14 Null Convention Logic Design Entry Example library ncl; use ncl.ncl_logic.all,ncl.ack_logic.all; use ncl.ncl_components.all; entity enc_4_to_2 is port ( din: in ncl_logic_vector(4 downto 1); ack_in, reset: in ack_logic; ack_out : out ack_logic; dout: out ncl_logic_vector(2 downto 1)); end enc_4_to_2;

15. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 15 Null Convention Logic Design Entry Example architecture behave of enc_4_to_2 is signal b: ncl_logic_vector(2 downto 1); begin encode : process(din) begin... end process encode; ir1: ncl_register_ss generic map (width => 2, initial_value => -1, stages => 1) port map (datain => d, ki => ack_in, rst => reset, dataout => dout, ko => ack_out); end behave;

16. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 16 Null Convention Logic Synthesis RTL Synthesis RTL Synthesis Transform VHDL/Verilog to 3NCL netlist Transform VHDL/Verilog to 3NCL netlist Netlist contains just AND & INV gates Netlist contains just AND & INV gates Off-the-shelf synthesis tools Off-the-shelf synthesis tools NULL values are treated as “don’t care” NULL values are treated as “don’t care” Logic optimizations Logic optimizations Dual-rail expansion Dual-rail expansion 3NCL netlist to 2NCL netlist 3NCL netlist to 2NCL netlist DIMS implementation of AND & INV gates DIMS implementation of AND & INV gates Produces a delay-insenstive circuit Produces a delay-insenstive circuit Logic optimizations Logic optimizations

17. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 17 Dual Rail NAND DIMS implementation [Ligthart et al., 2000]

18. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 18 Null Convention Logic Technology Mapping DIMS implementation inefficient DIMS implementation inefficient Techn. mapping on threshold gates Techn. mapping on threshold gates Circuit functionality fully described by set function of DIMS implementation Circuit functionality fully described by set function of DIMS implementation DIMS smoothing: Derive boolean network representing set function DIMS smoothing: Derive boolean network representing set function Threshold gates have specific set function Threshold gates have specific set function Perform logic optimization and map boolean network to available threshold gates Perform logic optimization and map boolean network to available threshold gates

19. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 19 Dual Rail NAND DIMS implementation Set function [Ligthart et al., 2000]

20. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 20 Null Convention Logic Threshold Gates Library of threshold gates by Theseus Library of threshold gates by Theseus all unate functions with up to 4 inputs all unate functions with up to 4 inputs

21. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 21 Specialized HDLs Think asynchronous & implement asynchronous Think asynchronous & implement asynchronous Low-level circuit specificitions Low-level circuit specificitions Petri-nets and STGs Petri-nets and STGs Used for modeling control circuits Used for modeling control circuits High-level languages High-level languages Typically based on Communicating Sequential Processes (CSP) Typically based on Communicating Sequential Processes (CSP) Tangram, Haste, Balsa Tangram, Haste, Balsa CHP CHP

22. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 22Balsa Asynchronous high-level HDL & complete synthesis framework Asynchronous high-level HDL & complete synthesis framework Based on Tangram system by Philips Based on Tangram system by Philips Open-Source: Developed at University of Manchester Open-Source: Developed at University of Manchester Syntax-directed compilation Syntax-directed compilation 1-to-1 mapping of language constructs to handshake circuit components 1-to-1 mapping of language constructs to handshake circuit components Allows experienced designer to easily envision the resulting circuit Allows experienced designer to easily envision the resulting circuit

23. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 23 Balsa Handshake Circuits Approx. 40 handshake components Approx. 40 handshake components Connected over channels Connected over channels Data path associated Data path associated Pure control channels (no data transferred) Pure control channels (no data transferred) Active ports initiate communication Active ports initiate communication Passive ports respond to request Passive ports respond to request Push channel Push channel Data flow from active to passive port Data flow from active to passive port Pull channel Pull channel Data flow from passive to active port Data flow from passive to active port

24. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 24 Example: Handshake Components Fetch (  ) Fetch (  ) Transfers data upon request Transfers data upon request Case (@) Case (@) Conditional control flow element Conditional control flow element Source: [Balsa Manual]

25. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 25 The Balsa Language Overview Similar to a typical imperative programming language Similar to a typical imperative programming language Strongly typed Strongly typed Circuit described with procedures Circuit described with procedures Like VHDL entity/architecture Like VHDL entity/architecture Parameters represent in/out channels Parameters represent in/out channels Procedure call like component instantiation Procedure call like component instantiation procedure foo (input i : byte; output o : byte) is -- Local declarations Begin -- Implementation end

26. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 26 The Balsa Language Types Types based on bit vectors Types based on bit vectors Numeric types Numeric types Unsigned: Range [0, 2 n -1] Unsigned: Range [0, 2 n -1] Signed: Range [-2 n-1, -2 n-1 -1] Signed: Range [-2 n-1, -2 n-1 -1] Enumerations Enumerations Named numeric values Named numeric values Records Records Arrays Arrays

27. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 27 The Balsa Language Operators Standard logic/arithmetic operators Standard logic/arithmetic operators Control operators Control operators Sequence operator (;) Sequence operator (;) Parallel composition (||) Parallel composition (||) Sync Command Sync Command Channel Operators Channel Operators Read (->) Read (->) Write (<-) Write (<-) Variable Assignment (:=) Variable Assignment (:=)

28. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 28 The Balsa Language Conditional Execution If statements If statements Case statements Case statements -- Sequential evaluation if then else if then end -- Concurrent evaluation if then | then end case x+y of 1.. 4, 11 then o <- x | 5.. 10 then o <- y else o <- z end

29. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 29 The Balsa Language Loops Iterative execution (while loop) Iterative execution (while loop) Structural iteration (for loop) Structural iteration (for loop) Hardware instantiated for each iteration Hardware instantiated for each iteration Comparable to “for... generate” in VHDL Comparable to “for... generate” in VHDL -- Simple while while then end -- Multiple guards while then | then end -- Sequential for for ; i in 1.. max_count then end -- Parallel for for || i in 1.. max_count then end

30. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 30 Example: 1-place Buffer (-- buffer1.balsa: Balsa program defining an 8 bit wide single place buffer --) import [balsa.types.basic] procedure buffer1 (input i : byte; output o : byte) is variable x : byte begin loop i -> x -- Input communication ; -- Sequence operator o <- x -- Output communication end

31. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 31 Example: 2-place Buffer (-- buffer2.balsa: a 2-place buffer using parallel composition --) import [balsa.types.basic] import [buffer1] procedure buffer2 (input i : byte; output o : byte) is channel c : byte begin buffer1 (i, c) || buffer1 (c, o) end

32. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 32 Example: Modulo-10 Counter import [balsa.types.basic] type C_size is nibble constant max_count = 9 procedure count10(sync aclk; output count: C_size) is variable count_reg : C_size variable tmp : C_size begin loop sync aclk; if count_reg /= max_count then tmp := (count_reg + 1 as C_size) else tmp := 0 end || count <- count_reg ; count_reg := tmp end -- loop end -- begin

33. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 33 Example: Modulo-10 Counter Source: [Balsa Manual]

34. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 34 References Taubin et al., Design Automation of Real-Life Asynchronous Devices and Systems, Foundations and Trends in Electronic Design Automation, 2007 Taubin et al., Design Automation of Real-Life Asynchronous Devices and Systems, Foundations and Trends in Electronic Design Automation, 2007 Cortadella et al., Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications, Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006 Cortadella et al., Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications, Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006 Ligthart et al., Asynchronous Design Using Commercial HDL Synthesis Tools, ASYNC 2000 Ligthart et al., Asynchronous Design Using Commercial HDL Synthesis Tools, ASYNC 2000 Edwards et al., Balsa: A Tutorial Guide, 2006 Edwards et al., Balsa: A Tutorial Guide, 2006

35. Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 35Conclusion/Summary EDA is an important requirement for acceptance of asynchronous design EDA is an important requirement for acceptance of asynchronous design Need powerful design languages Need powerful design languages Need powerful tools Need powerful tools Active field of research Active field of research Presented flows: De-synchronization, NCL, Tangram/Balsa Presented flows: De-synchronization, NCL, Tangram/Balsa Allow for high-level modeling (RTL) Allow for high-level modeling (RTL) Proven for real-life circuits Proven for real-life circuits