1. 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski 1 OverVoltage Protection Module for Power Supply System -overview – functionality -main components -architecture of OVP module -communication with MCU (microcontroller) -summary – time schedule

2. 2 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

3. 3 DHP_IO, DCD_DVDD DHP_CORE, DCD_AVDD ALL DOMAIN e.g. Digital, Analog, Gate, Steering Functionality (see Stefan paper v 1.0 from 24.7.2013) Serial readout by MCU Voltage monitor 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

4. AV2 VSource ST12 Gate_off ST9,10,11 Gate_on x 3 ST2 Clear_off ST1 Clear_on ST 16 VDRIFT ST13,14,15 CCG x 3 ST5 VBP (-3V,+5V) (-13V,-3V) (7V,25V) (0V,5V) ST7 VBulk (-12V,-5V)(-80V) (-10V,+1V) (0V,7V) (5V,15V) (1.8V)(1.6-2.0V) (0.9-1.4V)(1.6-2.0V) (0.35V) DV4 DVDD_DCD DV3 DVDD_DHPCORE AGND (Digital Ground) AV3 DCD_AmpLow DV2 DVDD_SW AV4 DCD_RefIn DV1 DVDD_DHPIO (1.0-1.3V) (1.6-2.0V) DGND (Digital Ground) SGND (Steering Ground) ST6 VGuard (-7V,0V) DEPFET GGND (Gate Ground) AV1 AVDD DCD ST4 SW_SUB <Gate ON (-80V) ST3 SW_ReIn SW_SUB+3.3V 4 Power Supply Domains

5. 5 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski Power Supply Scheme from White Book

6. 6 Digital Domain All voltages will be fixed by resistor networks !!! Gate Domain 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski OVP range > nominal range

7. 7 Analog Domain Steering Domain All voltages will be fixed by resistor networks !!! 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

8. 8 Digital Domain OVP Status bits are sent to the uC, reset (re-enable) bits are sent to the domains. Digital Control of the Over Voltage Protection Board Analog Domain OVP Gate Domain OVP Steering Domain OVP OV STATUS REGISTER Xilinx CPLD OVP_IO.A(0-5) OVPIO.MUX_OUT OVP_IO.STATUS from PS to Front_End 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski8

9. 9 Nodes of Digital and Analog Voltages DCD_DVDD,SW_DVDD,DHP_IO,DHP_CORE,DCD_AVDD,VSOURCE,REF_IN Vin Vout LFAULTN LSHDN Sense+ Sense- -5V Gain Selectable Amplifier -5V 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski R1 R2

10. 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski10 Simulated with SPICE and tested with 15 m cable (one channel). PS Regulator OVP LOAD

11. 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski11 INPUT – Over Voltage does not propagate to Load ! OUTPUT FAULT TMR

12. OR Nodes of Gate and Steering Voltages - Voltage Monitor CLEAR ON, CLEAR OFF, VBP, VGUARD, VBULK, GATE OFF, GATE ON, VCCG, VDRIFT Vin (from -50V to +50V)Vout ON / OFF UFAULTN Sense+ Sense- X 0.1 5V + - INA146 Promgrammable Gain Difference Amplifier R1 R2 R3 Solid State Relay from -5V to +5V 1225-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

13. 13 Simulated with SPICE.

14. 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski14 Gate_Off from -3V to +5V when out of rage

15. 15 Vin (1-4)Vout(1-4) Off/Reset Analogl Domain DCD_AVDD Fault Off/Reset VSOURCE Fault Off/Reset REF_IN Fault Off/Reset AMP_LOW (?) Hardwired Logic Xilinx Fault 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

16. 16 Vin (1-4)Vout(1-4) Fault Off/Reset Digital Domain DCD_DVDD Fault Off/Reset SW_DVDD Fault Off/Reset DHP_IO Fault Off/Reset DHP_CORE Hardwired Logic Xilinx 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

17. 17 Vin (1-8)Vout(1-8) Fault Off/Reset Hardwired Logic Xilinx Off/Reset Fault Steering Domain Clear Off Clear On VGuard SW_SUB < Gate On 1 Bulk 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski SW_SUB < Gate On 2 SW_SUB < Gate On 3

18. 18 Vin (1-8)Vout(1-8) Fault Off/Reset Hardwired Logic Xilinx Off/Reset Fault Gate Domain CCG2 Gate OFF VDrift CCG1 CCG3 GateON2-SW_SUB>0 GateON1-SW_SUB>0 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

19. 19 Communication with MicroController Unit

20. OverVoltage Protection control 6 input bits of the multiplexer address A[5:0]; 1 output data bit; 1 output status bit; 2 input shutdown lines SHTDN1, SHTDN2; input serial clock and serial data (I2C). OVP logic should contain an error register (failure bits of all channels); OVP logic may contain a control register (mask bits for all channels); the mask bit should make the given channel permanently open. OVP logic should be informed about entering the “active” state, otherwise the 2912 window mode of operation would be not feasible. Simple usage report failure on the status bit (OR of all error register bits) - OVP_IO.STAUS; use A[5] as a read/write selector (0-> read, 1-write) - OVP_IO.A5 ; read the error register contents with A[5]=0 and A[4:0] used as a channel address; set the control register (masks) using serial shift-in (I2C lines or...) with A[5]=1; use SHTDN1 as an indication of the “active” state. use shtdwn2 as the reset signal for all error bits. 2025-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

21. Switch-on scenario (?...) power-on the OVP Module; mask all „2912” channels (make them “opened”, without “in-window” control); wait for an “active” signal from the PS unit; on the “active” arrival remove all „2912” masks and go into normal control state. 2125-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

22. 22 OVP_IO.A5OVP_IO.A4OVP_IO.A3OVP_IO.A2OVP_IO.A1OVP_IO.A0 01toggle bit(010)0000CLEAR_FF 11toggle bit(010)000PRESET_FF 21toggle bit(010)0010ENABLE OVP 31toggle bit(010)0011DISABLE OVP 41toggle bit(010)0100 51 0101 61 0110 71 0111 81 1000 91 1001 101toggle bit(010)1010 111toggle bit(010)1011 121toggle bit(010)1100 131toggle bit(010)1101 141toggle bit(010)1110 151toggle bit(010)1111 Communication with Microcontroller OVP_IO.A(0-5), OVP_IO.MUX_OUT,OVP_IO.STATUS Commands Write Operation 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski OVP_IO.A0 OVP_IO.A1 OVP_IO.A2 OVP_IO.A3 OVP_IO.A4 OVP_IO.A5 OVP_IO.MUX_OUT OVP_IO.STATUS

23. 23 OVP_IO.A(0-5) OVPIO.MUX_OUT OVP_IO.STATUS Fault OVPIO.MUX_OUT OVP_IO.A(0-5) from Surge Stopper or Voltage Monitor Clear FF Preset FF Enable OVP Disable OVP Read Operation 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

24. PCB of OVP Module: four layers PCB with thick (100um-70um-70um-100um) copper; built from the “reusable blocks” to facilitate re-design. 24 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

25. 25 Summary: 1.waiting for PCB – middle of June 2.components for prototype are ordered 3.hand made assembly of prototype and tests – in July 4.integration with PS system – August-Semtember in Munich if OK go to 5 if NO go to 1 5. starting of mass production 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta

26. 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski26 Thank you !

27. 27 Backup slides 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

28. 2825-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

29. 2925-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

30. 3025-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski

31. 31

32. 25-28 May 2014 Seeon Piotr Kapusta, Bartlomiej Kisielewski32