1. Sommario dell'incontro Academia meets Industries (LNF), nell'ambito del progetto AIDA G. Di Pirro

2. Advanced European Infrastructures for Detectors at Accelerators (AIDA). Started 2011 More than 80 institutes and laboratories from 23 European countries are involved in the project 8 million Euros from the EU under the FP7 Research Infrastructures program. It aims to upgrade, improve and integrate key European research infrastructures and develop advanced detector technologies for future particle accelerators (LHC upgrade, Linear Colliders, Neutrino facilities and Super-B factories) in line with the European Startegy for Particle Physics. The European researchers from outside the project can benefit from EU Transnational Access funding to access AIDA test beams and irradiation facilities. The project is coordinated by CERN

3. The particle detectors developed in the AIDA project will be used in a planned upgrade to the LHC, and the proposed International Linear Collider machine, which will study with higher precision the Standard Model of Physics and beyond, Neutrino facilities to probe the mysteries of elusive neutrino particles and Super-B factories to understand the matter- antimatter asymmetry in the Universe.

4. The AIDA project is divided into 3 main activities: Networking, Joint Research and Transationa Access. These strands are further subdivided into work packages. The networking activity will study promising new technologies such as 3D detectors and electronics to build these detectors as well as specifying what the technological needs of the future are. Interactions with appropriate industrial partners will also be planned. The joint research activity will see many institutes working together to improve beam lines to test particle detectors. The equipment and technology needed to produce these detectors will also be upgraded. The transnational access activity will see access to beam lines at CERN and DESY and irradiation facilities across Europe for testing particle detectors opened up to new users. Experts in this area can contribute to the field with their findings by using these test facilities.

5. Already the technology used in particle detectors has been successfully transferred to areas such as medical imaging. Positron Emission Tomography (PET), Computer Tomography (CT) X-ray scanners and other X-ray imaging devices found in hospitals have been developed from technology originally developed for particle detectors. Detector technology is also being applied to radioactive waste monitoring and the transport sector for container scanning systems and to detect hazardous material in baggage. AIDA will work closely with industry to develop new technology to lead to new applications for society.

6. Work Package 2: Common Software Tools The goal of this task is to develop a set of software tools (computer programs which can simulate what happens in detectors) which can describe the geometry of the detector, the material it is made from and different ways of detecting particles. Events in particle detectors will be simulated with these tools and then analysed. Work Package 3: Microelectronics and interconnection technology the goal is to bring together the community and use the collective effort to build common demonstrators which can be used to test the different technologies proposed by industry for such connections. Both sensor and electronics read-out wafers will be produced including all the specific criteria needed for the 3D interconnection.

7. Work Package 4: Relations with Industry New particle detector technologies can move from Research and Development to larger scale production for our needs in experiments only with a relationship with industry. In this Work Package several workshops will be set up to discuss key technology areas within detector physics for the next ~10 years. They will bring together representatives from future accelerator projects, the particle physics community, industrial partners and experts from related fields of physics who use similar technologies. Work Package 8: Improvement and Equipment of Irradiation and Test Beam lines Coordination and Communication Test beams infrastructure at CERN and Frascati Upgrade of PS proton and mixed-field irradiation facilities at CERN Qualification of components and common database Coordination of combined beam tests and common DAQ

8. Work Package 9: Advanced Infrastructures for Detector R&D Micro-pattern gaseous tracking devices (MPGDs) are new technology still in the R&D phase. Silicon pixel detectors are used in the inner most layers of particle detectors. Development of detectors with extremely high precision is taking place in future collider experiment projects. The performance of the reconstruction algorithms developed in Work Package 2 for the jets are based on excellent reconstruction of both charged and neutral particles. New promising algorithms to reconstruct jets are under study in Work Package 2. They are based on a very granular calorimeter being able to separate the energy deposit of each individual particle within the jet (in association with a charged particle measurement). Transnational Access Within the Transnational Access elegibility criteria, users can apply to access test beam facilities at CERN and DESY, as well as irradiation facilities at CERN and across Europe.

9. AIDA - Academia meets Industry: Advanced interconnections for chip packaging in future detectors Frascati 8-9 Aprile 2012

10. Necessità della comunità scientifica Alte energie Astroparticelle Detector per X-RAY Medical imaging.

11. The Tracking Detector Commandments 1.Thou shalt minimize mass 2.Thou shalt have high digital bandwidth 3.Thou shalt be radiation hard 4.Thou shalt not dissipate power 5.Thou shalt have complex functionality 6.Thou shalt maximize position resolution (minimize pitch) 7.Thou shalt minimize dead regions 8.Thou not covet thy neighbors signals 9.Thou must be affordable 10.Thou shalt have fast analog signal processing (396 ns -> 25ns -> 1- 2 ns -> 100 ps) 11

12. Detectors and Electronics Designed for Low Earth Orbit Challenges: Static loads: 40+10+10g Vibration: 6.8g rms Depressurization: 1 to 0 atmosphere in 2 min. 0 g & Vacuum: No convection, outgassing Operational Range: -20 to +50 °C operational Ionizing Radiation: ~ 1 Krad/year Heavy Ions (SEE): latch ups, bit flips Atomic O, Solar UV: Etching & Aging MM/OD(Space Junk): Impact Electromag. Compat: with satellite, within the instrument NO ACCESS

13. Electronics Designed for Low Earth Orbit Challenges: Solutions: Static loads: Mechanical Design Vibration: Mechanical Design Depressurization: Mechanical Design 0 g & Vacuum: Materials, Thermal Management Operational Range: Components, Thermal Management Ionizing Radiation: Component Selection Heavy Ions (SEE): Comp Sel, Beam Tests, Protection Atomic O, Solar UV: Materials MM/OD(Space Junk): Mechanical Design Electromag. Compat: Shielding, Grounding, Test NO ACCESS: Redundancy, Reliability, TEST, TEST, TEST Process validated by several running experiments: PAMELA, Agile, Fermi, AMS-02

14. TSV-based Vertical Interconnections Descrizione dello stato dell’arte della tecnologia TSV (Through-Silicon Vias ) sia dal punto di vista accademico che da quello industriale

15. © CEA. All rights reserved TSV state of the art / AIDA workshop / 08-09/04/2013 / D.Henry | 15  In electronics, a 3D integrated circuit is a chip in which two or more layers of active electronic components are integrated vertically into a single circuit, component or system. Introduction : What is 3D Integration ?  3D Integration key drivers :  Form factor decrease  Performances improvement  Heterogeneous integration  Cost decrease Interposer / substrate Logic Memory passives

16. © CEA. All rights reserved TSV state of the art / AIDA workshop / 08-09/04/2013 / D.Henry | 16 Introduction : Why do we need 3D Integration ?  To solve the following issues :  Form factor decrease :  X & Y axis  Z axis  Performances improvement  Decrease R, C, signal delay  Increase device bandwidth  Decrease power consumption  Heterogeneous integration  Integration of heterogeneous components in the same system  Cost decrese  Si surface decrease  Reuse of existing Packaging, BEOL & FEOL lines The key technology of 3D integration is TSV

17. © CEA. All rights reserved TSV state of the art / AIDA workshop / 08-09/04/2013 / D.Henry | 17 Product example : Passive interposer / TSV first Chip A Chip B Organic substrate Chip Si-IP TSV Cu Pillar  Features  Cu TSV, AR10  2 to 4 layers routing, Damascene thick copper, L/W 0.5/0.5 x 1.4μm  Temporary bonding  Thinning, Stress Monitoring, Warp Management Under- fill Ken Miyairi, Masahiro Sunohara, Jean Charbonnier et al, IMAPS, San Diego 09/2012

18. © CEA. All rights reserved TSV state of the art / AIDA workshop / 08-09/04/2013 / D.Henry | 18 Product example : Active interposer – Partitioning / TSV middle Cu RDL Cu TSV BEOL Cu TSV  TSV    Top - Digital Bottom - Analog BGA  Die - die connection  Die - BGA connection 3D Integration of a Wireless product with Design Partitioning G. Druais et al., 3DIC 2012  Wide I/O  SDRAM JEDEC memory standard released Jan. 2012  TSV’s  Ø 10 μm, AR 8, Pitch 40 μm, Number 1016  Compatible with FD-SOI  Chip to Chip Cu Pillars  Ø20 μm, Height 20 μm, Pitch 40 μm, Number 1016  SoC to Substrate Cu Pillars  Ø55 μm, Height 40 μm, Pitch >200 μm, Number 933  FBGA Package  Size 12x12mm, Ball Pitch 0.4mm,Ball Matrix 29x29, 1.2 mm thickness

19. © CEA. All rights reserved TSV state of the art / AIDA workshop / 08-09/04/2013 / D.Henry | 19 Product example : memory on application processor – TSV middle Source : J. Michailos / ST Micro / 2013

20. © CEA. All rights reserved TSV state of the art / AIDA workshop / 08-09/04/2013 / D.Henry | 20 Product example : Ultra thin 3D capacitors stacking – TSV last Thinned 3D capacitors interposer TSV PCB or Si wafer <100µm solder Sample of IPD of 250nF/mm2 thinned at 60µm Low profile 3D-IPD for Advanced Wafer Level Packaging S. Bellenger,et al.IMAPS Minapad 2011 Courtesy of IPDIA

21. © CEA. All rights reserved TSV state of the art / AIDA workshop / 08-09/04/2013 / D.Henry | 21 Product example : TSV for ATLAS Readout chip – TSV last Source : J. Wolf / TSV summit / January 2013  Tapered TSV with Cu liner

22. © CEA. All rights reserved TSV state of the art / AIDA workshop / 08-09/04/2013 / D.Henry | 22 Product example : TSV for Medipix project – TSV last  Product : XRay detector for medical applications  Project started On June 2011  First wafers delivered on January 2012 Single chip Design Wafer view TSV Back side UBM Medipix wafer after front side UBM Technology TSV Electrical Tests

23. © CEA. All rights reserved TSV state of the art / AIDA workshop / 08-09/04/2013 / D.Henry | 23

24. © CEA. All rights reserved TSV state of the art / AIDA workshop / 08-09/04/2013 / D.Henry | 24

25. Through-Silicon Vias (TSV) Descrizione tool di sviluppo di sistemi integrati 3D. Cad Metodi di disegno

26. Integrazione di sensori con elettronica di acquisizione. Tecnologia per la realizzazione delle interconnessioni verticale

27. Conclusioni Manca una “killer application” per una produzione di massa Costi per piccole produzioni Tecnologia pronta