COMBINATIONAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUITS
UNIT II COMBINATIONAL LOGIC CIRCUITS

Combinational vs. Sequential Logic
Output = f ( In ) Output = f ( In, Previous In )

Static Complementary CMOS
Pull-up network (PUN) and pull-down network (PDN) VDD F(In1,In2,…InN) In1 In2 InN PUN PDN … PMOS transistors only pull-up: make a connection from VDD to F when F(In1,In2,…InN) = 1 NMOS transistors only pull-down: make a connection from F to GND when F(In1,In2,…InN) = 0 One and only one of the networks (PUN or PDN) is conducting in steady state (output node is always a low-impedance node in steady state) Why PUN of PMOSs only and PDN of NMOSs only ? (Next slide) PUN and PDN are dual logic networks

NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high

PMOS Transistors in Series/Parallel Connection

Threshold Drops VDD VDD PUN VDD 0  VDD 0  VDD - VTn VGS CL CL PDN
Why PMOS in PUN and NMOS in PDN … threshold drop NMOS transistors produce strong zeros; PMOS transistors generate strong ones PDN VDD  0 VDD  |VTp| VGS CL CL D S VDD S D

Complementary CMOS Logic Style

Example Gate: NAND

Example Gate: NOR

Complex CMOS Gate D A B C OUT = D + A • (B + C)
Shown synthesis of pull up from pull down structure

Constructing a Complex Gate

Elmore Delay ON transistors look like resistors
Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder

Example: 2-input NAND Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

Estimate the worst case falling propagation delays of a 2-input NAND driving h identical gates
The worst case occurs when the node x is already charged up to nearly Vdd through the top nMOS Suppose A = 1, B = 0, then Y = 1, node X is nearly VDD Now change inputs to A=B=1 both node Y and node X need to discharge

Example: 2-input NAND Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates.

Delay Components Delay has two parts
Parasitic delay, gate driving its own internal diffusion capacitance 6 or 7 RC Independent of load Effort delay, depends on the ration of external load capacitance to input capacitance, Effort delay changes with transistor width Proportional to load capacitance Logical effort and Electrical effort

Contamination Delay Best-case (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously, the output should be pulled up in half the time tcdr = (R/2)(6+4h)C

CIRCUIT FAMILIES Static CMOS Ratioed Circuits
Cascode Voltage Switch Logic (CVSL) Dynamic Circuits Pass-transistor Circuits

Static CMOS Circuits

Static CMOS Circuits In Static CMOS circuits with n inputs, 2n transistors are needed. nMOS block is a dual of the pMOS block. What ever is in series in nMOS, appears in parallel in pMOS and vice versa. CMOS gates consume power only during the transition of inputs.

Static complementary gate structure
Pull-up and pull-down networks VDD pull-up network out inputs Pull-down network VSS 7

Pull-up/pull-down network design
Pull-up and pull-down networks are duals. To design one gate, first design one network, then compute dual to get other network. 13

Inverter 8

CMOS Logic Style Construction

Example Gate: NAND

BUBBLE PUSHING

Compound Gates - AOI/OAI gates
AOI = and/or/invert; OAI = or/and/invert. Implement larger functions. Pull-up and pull-down networks are compact: smaller area, higher speed than NAND/NOR network equivalents. 11

AOI example invert or and 12

AOI CMOS Gate AOI complex CMOS gate can be used to directly implement a sum-of-products Boolean function The pull-down N-tree can be implemented as follows: Product terms yield series-connected NMOS transistors Sums are denoted by parallel-connected legs The complete function must be an inverted representation The pull-up P-tree is derived as the dual of the N-tree

OAI CMOS Gate An Or-And-Invert (OAI) CMOS gate is similar to the AOI gate except that it is an implementation of product-of-sums realization of a function The N-tree is implemented as follows: Each product term is a set of parallel transistors for each input in the term All product terms (parallel groups) are put in series The complete function is again assumed to be an inverted representation The P-tree can be implemented as the dual of the N-tree Note: AO and OA gates (non-inverted function representation) can be implemented directly on the P-tree if inverted inputs are available

Properties of CMOS Gates

Ratioed Circuits Pseudo-nMOS Circuits Ganged CMOS
Source-Follower Pull-up Logic (SFPL) 13 34

Figure 1 General structure of a pseudo-nMOS logic gate
Pseudo-nMOS Circuits Adding a single pFET to otherwise nFET-only circuit produces a logic family that is called pseudo-nMOS Less transistor than CMOS For N inputs, only requires (N+1) FETs Pull-up device: pFET is biased active since the grounded gate gives VSGp = VDD Pull-down device: nFET logic array acts as a large switch between the output f and ground However, since the pFET is always biased on, VOL can never achieve the ideal value of 0 V A simple inverter using pseudo-nMOS as Figure 2 Figure 1 General structure of a pseudo-nMOS logic gate Figure 2 Pseudo-nMOS inverter

Ganged CMOS (Symmetric Circuits)
B C Z Inverters ganged together to perform a function. NOR gate ; Z = A+B+C

Source-Follower Pull-up Logic (SFPL)
SFPL is a variation on pseudo-NMOS whereby the load device is an N pull-down transistor and N source-follower pull-ups are used on the inputs. N pull-up transistors can be small limiting input capacitance N transistors are also duplicated as pull-down devices in order to improve the fall time Rise time is determined by the P1 inverter pull-up transistor when all inputs are low SFPL is useful for high fan-in NOR logic gates R. W. Knepper SC571, page 5-25

Cascode Voltage Switch Logic (CVSL)
Differential type of logic circuit where both true and complement inputs are required. N pull down tree are the dual of each other. P pull-up devices are cross-coupled to latch output.. Both true and complement outputs are obtained.

Basic Structure of CVSL
Q a b ... Q a b c

Dynamic CMOS Logic Logic function is implemented by the PDN only
No. of transistors is N+2 Smaller in area than static CMOS Full swing outputs (VOL = gnd and VOH = VDD) Non-ratioed Faster switching speed Power dissipation should be better Needs precharge clock. 13 40

Dual-Rail Domino Domino only performs noninverting functions:
AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem Takes true and complementary inputs Produces true and complementary outputs sig_h sig_l Meaning Precharged 1 ‘0’ ‘1’ invalid

Example: AND/NAND Given A_h, A_l, B_h, B_l
Compute Y_h = A * B, Y_l = ~(A * B)

Example: AND/NAND Given A_h, A_l, B_h, B_l
Compute Y_h = A * B, Y_l = ~(A * B) Pulldown networks are conduction complements

Example: XOR/XNOR Sometimes possible to share transistors

TRANSMISSION GATES NMOS pass transistor passes a strong 0 and a weak 1. PMOS pass transistor passes a strong 1 and a weak 0. Combine the two to make a CMOS pass gate which will pass a strong 0 and a strong 1.

TRANSMISSION GATE

PROBLEMS WITH TRANSMISSION GATES
No isolation between the input and output. Output progressively deteriorates as it passes through various stages. However designs get simplified.

Multiplexer

XOR gate

Transmission Gates N-Channel MOS Transistors pass a 0 better than a 1
P-Channel MOS Transistors pass a 1 better than a 0 This is the reason that N-Channel transistors are used in the pull-down network and P-Channel in the pull-up network of a CMOS gate. Otherwise the noise margin would be significantly reduced.

Transmission Gates Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well symbols

Transmission Gates Implementing XOR gates
With NAND gates and inverters: With transmission gates: Why would one of these circuits be preferable to the other?

Transmission Gates Implementing a multiplexer with transmission gates:
When S = 0, input X1 is connected to the output Y When S = 1, input X2 is connected to the output Y

Pass Transistors Transistors can be used as switches

Pass Transistor Pass-transistor circuits are formed by dropping the PMOS transistors and using only NMOS pass transistors In this case, CMOS inverters (or other means) must be used periodically to recover the full VDD level since the NMOS pass transistors will provide a VOH of VDD – VTn in some cases The pass transistor circuit requires complementary inputs and generates complementary outputs to pass on to the next stage

Pass Transistor This figure shows a simple XNOR implementation using pass transistors: If A is high, B is passed through the gate to the output If A is low, -B is passed through the gate to the output

Pass Transistor At right,
(a) is a 2-input NAND pass transistor circuit (b) is a 2-input NOR pass transistor circuit Each circuit requires 8 transistors, double that required using conventional CMOS realizations

Pass Transistor Pass-transistor logic gate can implement Boolean functions NOR, XOR, NAND, AND, and OR depending upon the P1-P4 inputs, as shown below. P1,P2,P3,P4 = 0,0,0,1 gives F(A,B) = NOR P1,P2,P3,P4 = 0,1,1,0 gives F(A,B) = XOR P1,P2,P3,P4 = 0,1,1,1 gives F(A,B) = NAND P1,P2,P3,P4 = 1,0,0,0 gives F(A,B) = AND P1,P2,P3,P4 = 1,1,1,0 gives F(A,B) = OR Circuit can be operated with clocked P pull-up device or inverter-based latch

Pass Transistor Logic Families
Complementary Pass Transistor Logic Double Pass Transistor Logic

Complementary Pass-Transistor Logic (CPL)

Basic logic functions in CPL

CPL Logic XOR gate Sum circuit
CPL provides an efficient implementation of XOR function

Full Adder Design III Complementary Pass Transistor Logic (CPL)
Slightly faster, but more area

Double Pass-Transistor Logic (DPL):
AND/NAND XOR/XNOR

XOR One bit full-adder: Sum circuit

DPL Full Adder The critical path traverses two transistors only (not counting the buffer)

EE141 Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors

Dynamic Gate Out Clk A B C Clk Out CL In1 In2 PDN In3 Clk Mp Me Mp Me
EE141 Dynamic Gate Out Clk A B C Mp Me Clk Mp Out CL In1 In2 PDN In3 Clk Me For class handout Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1)

Dynamic Gate Out Clk A B C off Clk on 1 Out CL ((AB)+C) In1 In2 PDN
EE141 Dynamic Gate Out Clk A B C Mp Me off Clk Mp on 1 Out CL ((AB)+C) In1 In2 PDN In3 Clk Me off For lecture Evaluate transistor, Me, eliminates static power consumption on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)

EE141 Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL This behavior is fundamentally different than the static counterpart that always has a low resistance path between the output and one of the power rails.

Properties of Dynamic Gates
EE141 Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL CL being lower also contributes to power savings

Properties of Dynamic Gates
EE141 Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between VDD and GND (including Psc) no glitching higher transition probabilities extra load on Clk PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn low noise margin (NML) Needs a precharge/evaluate clock

Dynamic Logic Dynamic gates uses a clocked pMOS pullup
Two modes: precharge and evaluate

The Foot What if pulldown network is ON during precharge?
Use series evaluation transistor to prevent fight.

Logical Effort

Issues in Dynamic Design 1: Charge Leakage
EE141 Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out CL A Evaluate VOut Clk Me Precharge leakage sources are reverse-biased diode and the sub-threshold leakage of the NMOS pulldown device. Charge stored on CL will leak away with time (input in low state during evaluation) Requires a minimum clock rate - so not good for low performance products such as watches (or when have conditional clocks) PMOS precharge device also contributes some leakage due to reverse bias diode and subthreshold conduction that, to some extent, offsets the leakage due to the pull down paths. Leakage sources Dominant component is subthreshold current

Solution to Charge Leakage
EE141 Solution to Charge Leakage Keeper Clk Mp Mkp CL A Out B Clk Me During precharge, Out is VDD and inverter out is GND, so keeper is on During evaluation if PDN is off, the keeper compensates for drained charge due to leakage. If PDN is on, there is a fight between the PDN and the PUN - circuit is ratioed so PDN wins, eventually Note Psc during switching period when PDN and keeper are both on simultaneously Same approach as level restorer for pass-transistor logic

Issues in Dynamic Design 2: Charge Sharing
EE141 Issues in Dynamic Design 2: Charge Sharing Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness Clk Mp Out CL A CA B=0 CA initially discharged and CL fully charged. CB Clk Me

Charge Sharing Example
EE141 Charge Sharing Example Clk Out CL=50fF A A Ca=15fF B Cb=15fF B B !B Cc=15fF Cd=10fF Out = A xor B xor C What is the worst case change in voltage on node Out - assume all inputs are low during precharge and all internal capacitances are initially 0V Worst case is obtained by exposing the maximum amount of internal capacitance to the output node during evaluation. This happens when !A B C or A !B C 30/(30+50) * 2.5 V = 0.94 V so the output drops to = 1.56 V C C Clk

Charge Sharing V Clk M Out C A M X C B = M C Clk M DD p L a a b b e
EE141 Charge Sharing V DD Clk M p Out C L A M a X C a B = M b C b Clk M e

Solution to Charge Redistribution
EE141 Solution to Charge Redistribution Clk Clk Mp Mkp Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

Issues in Dynamic Design 3: Backgate Coupling
EE141 Issues in Dynamic Design 3: Backgate Coupling Clk Mp Out1 =1 Out2 =0 CL1 CL2 In A=0 B=0 Due to capacitive backgate coupling between the internal and output node of the static gate and the output of the dynamic gate, Out1 voltage reduces Clk Me Dynamic NAND Static NAND

Backgate Coupling Effect
EE141 Backgate Coupling Effect Out1 Voltage Clk Out1 overshoots Vdd (2.5V) due to clock feedthrough And Out2 never quite makes it to GND Out2 In Time, ns

Issues in Dynamic Design 4: Clock Feedthrough
Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. Clk Mp Out CL A B Clk Danger is that signal levels can rise enough above VDD that the normally reverse-biased junction diodes become forward-biased causing electrons to be injected into the substrate. Me

Clock Feedthrough Clock feedthrough Clk Out In1 In2 In3 In & Clk In4
Voltage In4 Out Clk Time, ns Clock feedthrough

Other Effects Capacitive coupling Substrate coupling
EE141 Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce)

Cascading Dynamic Gates
EE141 Cascading Dynamic Gates V Clk Clk Clk Mp Mp Out2 Out1 In In Out1 VTn Clk Clk Me Me Out2 V Out2 should remain at VDD since Out1 transitions to 0 during evaluation. However, since there is a finite propagation delay for the input to discharge Out1 to GND, the second output also starts to discharge. The second dynamic inverter turns off (PDN) when Out1 reaches VTn. Setting all inputs of the second gate to 0 during precharge will fix it. Correct operation is guaranteed (ignoring charge redistribution and leakage) as long as the inputs can only make a single 0 -> 1 transition during the evaluation period t Only 0  1 transitions allowed at inputs!

Monotonicity Dynamic gates require monotonically rising inputs during evaluation 0 -> 0 0 -> 1 1 -> 1 But not 1 -> 0

Monotonicity Woes But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another!

Domino Logic Clk Clk Out1 Out2 In1 In4 PDN In2 PDN In5 In3 Clk Clk Mp
EE141 Domino Logic Clk Mp Mkp Clk Mp Out1 Out2 1  1 1  0 0  0 0  1 In1 In4 PDN In2 PDN In5 In3 Ensures all inputs to the Domino gate are set to 0 at the end of the precharge period. Hence, the only possible transition during evaluation is 0 -> 1 Clk Me Clk Me

Domino Gates Follow dynamic stage with inverting static gate
Dynamic / static pair is called domino gate Produces monotonic outputs

Domino Optimizations Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic

Dual-Rail Domino Domino only performs noninverting functions:
AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem Takes true and complementary inputs Produces true and complementary outputs sig_h sig_l Meaning Precharged 1 ‘0’ ‘1’ invalid

Example: AND/NAND Given A_h, A_l, B_h, B_l Compute Y_h = AB, Y_l = AB
Pulldown networks are conduction complements

Example: XOR/XNOR Sometimes possible to share transistors

np-CMOS

NORA Logic

NP Domino

Zipper CMOS The NP-Domino or NORA logic is very susceptible to noise and leakage. Zipper Domino has the same structure, but the precharge transistors are left slightly ON during evaluation.

Leakage Dynamic node floats high during evaluation
Transistors are leaky (IOFF  0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds Use keeper to hold dynamic node Must be weak enough not to fight evaluation

Charge Sharing Dynamic gates suffer from charge sharing

Secondary Precharge Solution: add secondary precharge transistors
Typically need to precharge every other node Big load capacitance CY helps as well

Noise Sensitivity Dynamic gates are very sensitive to noise
Inputs: VIH  Vtn Outputs: floating output susceptible noise Noise sources Capacitive crosstalk Charge sharing Power supply noise Feedthrough noise And more!

Power Domino gates have high activity factors
Output evaluates and precharges If output probability = 0.5, a = 0.5 Output rises and falls on half the cycles Clocked transistors have a = 1 For a 4 input NAND, aCMOS = 3/16, aDynamic = 1/4 Leads to very high power consumption However, glitching does not occur in dynamic logic. The load capacitances are lower.

MODL It is often necessary to compute multiple functions where one is a subfunction of the other or shares a subfunction. One very typical example is the carry in addition:

MODL Carry Chains

MODL Beware of sneak paths. Certain inputs must be mutually exclusive.

Domino Summary Domino logic is attractive for high-speed circuits
1.3 – 2x faster than static CMOS But many challenges: Monotonicity, leakage, charge sharing, noise Widely used in high-performance microprocessors in 1990s when speed was king Largely displaced by static CMOS now that power is the limiter Still used in memories for area efficiency

POWER DISSIPATION Power is drawn from a voltage source attached to the VDD pin(s) of a chip. Instantaneous Power: Energy: Average Power:

Overview of Power Dissipation
Ptotal = Pdynamic+Pstatic Power Consumption (Pdynamic) Dynamic power Consumption Pdynamic = Pswitching + Pshortcircuit Switching load capacitances Short-circuit current Charging and discharging capacitors Short Circuit Power Consumption (Pshort-circuit) Short circuit path between supply rails during switching

Power Dissipation Sources
Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD Subthreshold leakage Gate leakage Junction leakage Contention current

Dynamic Power Dynamic power is required to charge and discharge load capacitances when transistors switch. One cycle involves a rising and falling output. On rising output, charge Q = CVDD is required On falling output, charge is dumped to GND This repeats Tfsw times over an interval of T Vdd Vin Vout CL fsw

Dynamic Power

Dynamic Power Suppose the system clock frequency = f
Let fsw = af, where a = activity factor If the signal is a clock, a = 1 If the signal switches once per cycle, a = ½ Dynamic gates: Switch either 0 or 2 times per cycle, a = ½ Static gates: Depends on design, but typically a = 0.1 Dynamic power:

Dynamic Power Pdynamic = Energy/per-transition  Transition rate
= CLVDD2 f0→1 = CL VDD2 P0→1 f = Ceff VDD2 f Ceff = effective capacitance = CL P0→1 Power dissipation is data dependent Function of Switching Activity Activity Factor (P0→1) Clock signal: P0→1(clk) = 1 Data signal: P0→1(data) < 0.5

Short Circuit Current When transistors switch, both nMOS and pMOS networks may be momentarily ON at once Leads to a blip of “short circuit” current. ~ 15% of dynamic power ~85% to charge capacitance CL NMOS and PMOS on Both transistors in saturation Long rise / fall times Slow input transition Increase short circuit current Make input signal transitions fast to save power! Vin Vout CL Vdd

Short Circuit Current Large capacitive load Small capacitive load V DD out C L in ISC≈IMAX ISC≈0 Because of finite slope of input signal, there is a period when both PMOS and NMOS device are “on” and create a path from supply to ground r 8 7 6 5 4 3 2 1 D E / E V DD = 5 V = 3.3 V W/L| P = 7.2 m m/1.2 N = 2.4 The power dissipation due to short circuit currents is minimized by matching the rise/fall times of the input and output signals.

Dynamic Power Reduction
Try to minimize: Activity factor Capacitance Supply voltage Frequency

Voltage Scaling Dual voltage supply Reduced internal voltage 1.2V
For low power operation External voltage Compatible IO voltage 3.3V To interface other ICs

Capacitance Minimization
Gate capacitance Fewer stages of logic Small gate sizes Wire capacitance Good floorplanning to keep communicating blocks close to each other Drive long wires with inverters or buffers rather than complex gates

Clock Gating The best way to reduce the activity is to turn off the clock to registers in unused blocks Saves clock activity (a = 1) Eliminates all switching activity in the block Requires determining if block will be used

Voltage / Frequency Run each block at the lowest possible voltage and frequency that meets performance requirements Voltage Domains Provide separate supplies to different blocks Level converters required when crossing from low to high VDD domains Dynamic Voltage Scaling Adjust VDD and f according to workload

Static power Dissipation
Power dissipation occurring when device is in standby mode As technology scales this becomes significant Leakage power dissipation Components: Reverse biased p-n junction Sub threshold leakage DIBL leakage Channel punch through GIDL Leakage Narrow width effect Oxide leakage Hot carrier tunneling effect

Source of Leakage Current

Leakage Sub-threshold current Transistor conducts below Vt
For sub-micron relevant VDD / Vt ratio smaller Can dominate power consumption! Especially in idle mode. Charge nodes fully to VDD! Discharge nodes completely to GND! Drain leakage current Reverse biased junction diodes Vout Vdd Sub-threshold current Drain junction leakage

Static Power Static power is consumed even when chip is quiescent.
Ratioed circuits burn power in fight between ON transistors Leakage draws power from nominally OFF devices

Subthreshold current Sub-threshold current increases exponentially
Subthreshold current can be reduced by increasing Vt Selective application of multiple threshold (low-Vt transistors on critical paths, high Vt transistors on other paths) Control Vt through the body voltage Sub-threshold current decreases in long channel transistors and increases in short channel

Sub-threshold Leakage Component

Gate Leakage Extremely strong function of tox and Vgs
Negligible for older processes Approaches subthreshold leakage at 65 nm and below in some processes An order of magnitude less for pMOS than nMOS Control leakage in the process using tox > 10.5 Å High-k gate dielectrics help Some processes provide multiple tox e.g. thicker oxide for 3.3 V I/O transistors Control leakage in circuits by limiting VDD

Junction Leakage From reverse-biased p-n junctions
Between diffusion and substrate or well Ordinary diode leakage is negligible Band-to-band tunneling (BTBT) can be significant Especially in high-Vt transistors where other leakage is small Worst at Vdb = VDD Gate-induced drain leakage (GIDL) exacerbates Worst for Vgd = -VDD (or more negative)

RATIOED CIRCUIT Pseudo-NMOS logic style PMOS as resistor
PDN as static CMOS logic Static current When output low Power consumption Even without switching activity

Static power Reduction
Reduce static power Selectively use ratioed circuits Selectively use low Vt devices Leakage reduction: stacked devices, body bias, low temperature

COMBINATIONAL LOGIC CIRCUITS

Similar presentations

Presentation on theme: "COMBINATIONAL LOGIC CIRCUITS"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

COMBINATIONAL LOGIC CIRCUITS

Similar presentations

Presentation on theme: "COMBINATIONAL LOGIC CIRCUITS"— Presentation transcript:

Similar presentations

About project

Feedback