1. Memory and Programmable Logic08
Memory and Programmable Logic

2. RAM: Random Access Memory
All sequential circuits depend upon the presence of memory.
A flip-flop can store one bit of information.
A register can store a single “word,” typically bits.
8, 16 (?)
Random Access Memory, or RAM, allows us to store even larger amounts of data.
The basic interface to memory.
How you can implement static RAM chips hierarchically.
This is the last piece we need to put together a computer!
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3. Introduction to RAM
Random-Access Memory (or RAM), provides large quantities of temporary storage in a computer system.
Remember the basic capabilities of a memory:
It should be able to store a value.
You should be able to read the value that was saved.
You should be able to change the stored value.
A RAM is similar, except that it can store many values, and access times for different locations are the same.
An address will specify which memory value we’re interested in.
Each value can be a multiple-bit word (e.g., 32 bits).
We’ll refine the memory properties as follows:
A RAM should be able to:
- Store many words, one per address
- Read the word that was saved at a particular address
- Change the word that’s saved at a particular address
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4. Picture of Memory
You can think of computer memory as being one big array of data.
The address serves as an array index.
Each address refers to one word of data.
You can read or modify the data at any given memory address, just like you can read or modify the contents of an array at any given index.
If you’ve worked with pointers in C or C++, then you’ve already worked with memory addresses.
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5. Memory as a Black-Box Memory Unit 2k words n bit per word
k address lines
Read
Write
n data input lines
Memory Unit
2k words
n bit per word
n data output lines
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6. Memory View - Logical Binary 0000000000 0000000001 0000000010
Memory Address
Binary
Decimal 1 2 •
1021
1022
1023
AACFLRZ0
Memory Content •
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7. Block diagram of RAM
2k x n memory
ADRS OUT
DATA CS WR k n
This block diagram introduces the main interface to RAM.
A Chip Select, CS, enables or disables the RAM.
ADRS specifies the address or location to read from or write to.
WR selects between reading from or writing to the memory.
To read from memory, WR should be set to 0.
OUT will be the n-bit value stored at ADRS.
To write to memory, we set WR = 1.
DATA is the n-bit value to save in memory.
This interface makes it easy to combine RAMs together, as we’ll see.
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8. Memory sizes We refer to this as a 2k x n memory.
There are k address lines, which can specify one of 2k addresses.
Each address contains an n-bit word.
For example, a 224 x 16 RAM contains 224 = 16M words, each 16 bits long.
The RAM would need 24 address lines.
The total storage capacity is 224 x 16 = 228 bits.
2k x n memory
ADRS OUT
DATA CS WR k n
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9. 228 bits / 8 bits per byte = 225 bytes
Size matters!
Memory sizes are usually specified in numbers of bytes (8 bits).
The 228-bit memory on the previous page translates into:
228 bits / 8 bits per byte = 225 bytes
With the abbreviations below, this is equivalent to 32 megabytes.
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10. Typical Memory Sizes Some typical memory capacities:  ??? !!!
PCs usually come with MB RAM.
PDAs have 8-64MB of memory.
Digital cameras and MP3 players can have 32MB or more of storage.
Many operating systems implement Virtual Memory, which makes the memory seem larger than it really is.
Most systems allow up to 32-bit addresses. This works out to 232, or about four billion, different possible addresses.
With a data size of one byte, the result is apparently a 4GB memory!
The operating system uses hard disk space as a substitute for “real” memory (VM).
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11. Reading RAM To read from this RAM, the controlling circuit must:
Enable the chip by ensuring CS = 1.
Select the read operation, by setting WR = 0.
Send the desired address to the ADRS input.
The contents of that address appear on OUT after a little while.
Notice that the DATA input is unused for read operations.
2k x n memory
ADRS OUT
DATA CS WR k n n 1
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12. Memory Read Cycle Timing Diagram Address valid T1 T2 T3 Data valid
(b) Read cycle
Clock
Memory
address
enable
Read/
Write
Data
output
Initiate read
50 nsec
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13. Writing RAM To write to this RAM, you need to:
Enable the chip by setting CS = 1.
Select the write operation, by setting WR = 1.
Send the desired address to the ADRS input.
Send the word to store to the DATA input.
The output OUT is not needed for memory write operations.
2k x n memory
ADRS OUT
DATA CS WR k n 1 1
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14. Memory Write Cycle Timing Diagram Data valid (a) Write cycle 20 nsec
Address valid
Clock
Memory
address
enable
Read/
Write
Data
input
Data valid
(a) Write cycle
Initiate writing
Latched
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15. Static Memory How can you implement the memory chip?
There are many different kinds of RAM.
We’ll start off discussing static memory, which is most commonly used in caches and video cards.
Later we mention a little about dynamic memory, which forms the bulk of a computer’s main memory.
Static memory is modeled using one latch (or FF) for each bit of storage.
Why use latches instead of flip flops?
A latch can be made with only two NAND or two NOR gates, but a flip-flop requires at least twice that much hardware.
In general, smaller is faster, cheaper and requires less power.
The tradeoff is that getting the timing exactly right is a pain.
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16. Starting with Latches
To start, we can use one latch to store each bit. A one-bit RAM cell is shown here.
Since this is just a one-bit memory, an ADRS input is not needed.
Writing to the RAM cell:
When CS = 1 and WR = 1, the latch control input will be 1.
The DATA input is thus saved in the D latch.
Reading from the RAM cell and maintaining the current contents:
When CS = 0 or when WR = 0, the latch control input is also 0, so the latch just maintains its present state.
The current latch contents will appear on OUT.
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17. My First RAM We can use these cells to make a 4 x 1 RAM.
Since there are four words, ADRS is two bits.
Each word is only one bit, so DATA and OUT are one bit each.
Word selection is done with a decoder attached to the CS inputs of the RAM cells. Only one cell can be read or written at a time.
Notice that the outputs are connected together with a single line!
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18. Connecting outputs together
In normal practice, it’s bad to connect outputs together. If the outputs have different values, then a conflict arises.
The standard way to “combine” outputs is to use OR gates (?) or muxes.
This can get expensive, with many wires and gates with large fan-ins.
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19. Those funny triangles The triangle represents a three-state buffer.
Unlike regular logic gates, the output can be one of three different possibilities, as shown in the table.
“Disconnected” means no output appears at all, in which case it’s safe to connect OUT to another output signal.
The disconnected value is also sometimes called high impedance or Hi-Z.
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20. Connecting Three-State Buffers Together
You can connect several three-state buffer outputs together if you can guarantee that only one of them is enabled at any time.
The easiest way to do this is to use a decoder!
If the decoder is disabled, then all the three-state buffers will appear to be disconnected, and OUT will also appear disconnected.
If the decoder is enabled, then exactly one of its outputs will be true, so only one of the tri-state buffers will be connected and produce an output.
The net result is we can save some wire and gate costs. We also get a little more flexibility in putting circuits together.
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21. Bigger and Better Here is the 4 x 1 RAM once again.
How can we make a “wider” memory with more bits per word, like maybe a 4 x 4 RAM?
Duplicate the stuff in the blue box!
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22. A 4 x 4 RAM
DATA and OUT are now each four bits long, so you can read and write four-bit words.
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23. Bigger RAMs from smaller RAMs
We can use small RAMs as building blocks for making larger memories, by following the same principles as in the previous examples.
As an example, suppose we have some 64K x 8 RAMs to start with:
64K = 26 x 210 = 216, so there are 16 address lines.
There are 8 data lines. 8 16
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24. Constructing a larger memory
We can put four 64K x 8 chips together to make a 256K x 8 memory.
For 256K words, we need 18 address lines.
The two most significant address lines go to the decoder, which selects one of the four 64K x 8 RAM chips.
The other 16 address lines are shared by the 64K x 8 chips.
The 64K x 8 chips also share WR and DATA inputs.
This assumes the 64K x 8 chips have three-state outputs. 8 16
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25. Analyzing the 256K x 8 RAM
There are 256K words of memory, spread out among the four smaller 64K x 8 RAM chips.
When the two most significant bits of the address are 00, the bottom RAM chip is selected. It holds data for the first 64K addresses.
The next chip up is enabled when the address starts with 01. It holds data for the second 64K addresses.
The third chip up holds data for the next 64K addresses.
The final chip contains the data of the final 64K addresses. 8 16
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26. Address ranges 11 1111 1111 1111 1111 (0x3ffff) to8 16
(0x3ffff) to
(0x30000)
(0x2ffff)
(0x20000)
(0x1ffff)
(0x10000)
(0x0ffff)
(0x00000)
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27. Making a wider memory
You can also combine smaller chips to make wider memories, with the same number of addresses but more bits per word.
Here is a 64K x 16 RAM, created from two 64K x 8 chips.
The left chip contains the most significant 8 bits of the data.
The right chip contains the lower 8 bits of the data. 16 8
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28. Getting to know Murphy
“Early in the '50s, with the advent of jet aircraft there was a debate as to whether a pilot could safely eject from the aircraft.  In order to find out whether a man could survive the stresses of ejection the Air Force undertook a study (USAF project MX981).  The study involved shooting a rocket sled down a track, accelerating its passenger to speeds in excess of 630 miles of hour and then suddenly stopping in 1.4 seconds, generating over 40g's.
One experiment involved a set of 16 accelerometers mounted in different parts of the subject's body.  There were two ways each sensor could be glued to its mount.  And of course, each was installed the wrong way! One of the engineers on the project, Edward A. Murphy, made the original pronouncement of Murphy's Law, "If there are two or more ways to do something, and one of those can result in catastrophe, then someone will do it." The test subject, Major John Paul's Stapp an Air Force flight surgeon leading the project, quoted Murphy in a press conference a few days later.  Within months, Murphy's Law had spread to various technical cultures connected to aerospace engineering and finally to Webster's dictionary in “ excerpt taken from .html
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29. Binary Cell Block Diagram Logic Diagram BC Output Input Select
Read/Write S
Read/Write
Select
Input
Output
Logic Diagram R
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30. Output data Cell Access Input data Word 2 2 x 4 Decoder Address inputsBC BC BC BC
Address
inputs
Word 1 BC BC BC BC
2 x 4
Decoder
Word 2 BC BC BC BC
Memory
enable EN
Word 3 BC BC BC BC
Read/Write
Output data
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31. 2D Decoding 1K-Word Memory5
32 decoder 1 . 1 2 . 12
binary address
X Y
decoder X . 31
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32. Address Multiplexing register decoder 8-bit row memory cell array
8-bit column
register
CAS 8
256
decoder
RAS
8-bit
row
register
256 x 256
memory
cell array
8-bit
address
8 x 256
decoder
Read/Write
Data in
Data
out
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33. Error Correction Murphy’s law: "If anything can go wrong, it will!"
Memory is no exception! Some bit will flip once in a while..
Your task, of course if you accept it, is to
Detect whether there is an error
Correct it, if possible
This slide will destroy itself in 5 seconds….
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34. Error Correction Use extra bits For instance append a parity bit
For more interesting methods read the related section of the book.
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35. Summary
A RAM looks like a bunch of registers connected together, allowing users to select a particular address to read or write.
Much of the hardware in memory chips supports this selection process:
Chip select inputs
Decoders
Tri-state buffers
By providing a general interface, it’s easy to connect RAMs together to make “longer” and “wider” memories.
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36. Other memories Some other kinds of memories.
Dynamic RAM is used for the bulk of computer memory.
Read-only memories and PLAs are two “programmable logic devices,” which can be considered as special types of memories.
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37. Dynamic memory in a nutshell
Dynamic Memory is built with capacitors.
A stored charge on the capacitor represents a logical 1.
No charge represents a logic 0.
However, capacitors lose their charge after a few milliseconds. The memory requires constant refreshing to recharge the capacitors. (That’s what’s “dynamic” about it.)
Dynamic RAMs tend to be physically smaller than static RAMs.
A single bit of data can be stored with just one capacitor and one transistor, while static RAM cells typically require 4-6 transistors.
This means dynamic RAM is cheaper and denser—more bits can be stored in the same physical area.
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38. SDRAM
Synchronous DRAM, or SDRAM, is one of the most common types of PC memory now.
Memory chips are organized into “modules” that are connected to the CPU via a 64-bit (8-byte) bus.
Speeds are rated in megahertz: PC66, PC100 and PC133 memory run at 66MHz, 100MHz and 133MHz respectively.
The memory bandwidth can be computed by multiplying the number of transfers per second by the size of each transfer.
PC100 can transfer up to 800MB per second (100MHz x 8 bytes/cycle).
PC133 can get over 1 GB per second.
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39. DDR-RAM A newer type of memory is Double Data Rate, or DDR-RAM.
It’s very similar to earlier SDRAM, except data can be transferred on both the positive and negative clock edges. For MHz buses, the effective memory speeds appear to be MHz.
This memory is confusingly called PC1600 and PC2100 RAM, because
200MHz x 8 bytes/cycle = 1600MB/s
266MHz x 8 bytes/cycle = 2100MB/s.
DDR-RAM has lower power consumption, using 2.5V instead of 3.3V like SDRAM. This makes it good for notebooks and other mobile devices.
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40. RDRAM
Another new type of memory called RDRAM is used in the Playstation 2 as well as some Pentium 4 computers.
The data bus is only 16 bits wide.
But the memory runs at 400MHz, and data can be transferred on both the positive and negative clock edges.
That works out to a maximum transfer rate of 1.6GB per second.
You can also implement two “channels” of memory, resulting in up to 3.2GB/s of bandwidth.
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41. Dynamic vs. Static Memory
In practice, dynamic RAM is used for a computer’s main memory, since it’s cheap and you can pack a lot of storage into a small space.
These days you can buy 512MB of memory for as little as $60.
You can also load a system with 2GB or more of memory.
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42. Dynamic vs. Static Memory
The disadvantage of dynamic RAM is its speed.
Transfer rates are 800MHz at best, which can be much slower than the processor itself.
You also have to consider latency, or the time it takes data to travel from RAM to the processor.
Real systems augment dynamic memory with small but fast sections of static memory called caches.
Typical processor caches range in size from 128KB to 320KB.
That’s small compared to a 128MB main memory, but it’s enough to significantly increase a computer’s overall speed.
You’ll study caches later on in CENG331 next semester.
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43. Read-Only Memory (ROM)
(a) Conventional symbol
(b) Array logic symbol
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44. Read-Only Memory
A read-only memory, or ROM, is a special kind of memory whose contents cannot be easily modified.
The WR and DATA inputs that we saw in RAMs are not needed.
Data is stored onto a ROM chip using special hardware tools.
ROMs are useful for holding data that never changes.
Arithmetic circuits might use tables to speed up computations of logarithms or divisions.
Many computers use a ROM to store important programs that should not be modified, such as the system BIOS.
PDAs, game machines, cell phones, vending machines and other electronic devices may also contain non-modifiable programs.
2k x n ROM
ADRS OUT CS k n
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45. Memories and functions
ROMs are actually combinational devices, not sequential ones!
You can’t store arbitrary data into a ROM, so the same address will always contain the same data.
You can think of a ROM as a combinational circuit that takes an address as input, and produces some data as the output.
A ROM table is basically just a truth table.
The table shows what data is stored at each ROM address.
You can generate that data combinationally, using the address as the input.
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46. Using Decoders
We can already convert truth tables to circuits easily, with decoders.
For example, you can think of this old circuit as a memory that “stores” the sum and carry outputs from the truth table on the right.
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47. ROM setup ROMs are based on this decoder implementation of functions.
A blank ROM just provides a decoder and several OR gates.
The connections between the decoder and the OR gates are “programmable,” so different functions can be implemented.
To program a ROM, you just make the desired connections between the decoder outputs and the OR gate inputs.
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48. ROM Example
Here are three functions, V2V1V0, implemented with an 8 x 3 ROM.
Blue crosses (X) indicate connections between decoder outputs and OR gates. Otherwise there is no connection.
V2 = m(1,2,3,4) V1 = m(2,6,7) V0 = m(4,6,7) A2 A1 A0
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49. The same example again …
Here is an alternative presentation of the same 8 x 3 ROM, using “abbreviated” OR gates to make the diagram neater.
V2 V1 V0 A2 A1 A0
V2 = m(1,2,3,4)
V1 = m(2,6,7)
V0 = m(4,6,7)
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50. Why is this a “Memory”?
This combinational circuit can be considered a read-only memory.
It stores eight words of data, each consisting of three bits.
The decoder inputs form an address, which refers to one of the eight available words.
So every input combination corresponds to an address, which is “read” to produce a 3-bit data output.
V2 V1 V0 A2 A1 A0
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51. ROMs vs. RAMs
There are some important differences between ROM and RAM.
ROMs are “non-volatile”—data is preserved even without power. On the other hand, RAM contents disappear once power is lost.
ROMs require special (and slower) techniques for writing, so they’re considered to be “read-only” devices.
Some newer types of ROMs do allow for easier writing, although the speeds still don’t compare with regular RAMs.
MP3 players, digital cameras and other toys use CompactFlash, Secure Digital, or MemoryStick cards for non-volatile storage.
Many devices allow you to upgrade programs stored in “flash ROM.”
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52. Programmable Logic Arrays
A ROM is potentially inefficient because it uses a decoder, which generates all possible minterms. No circuit minimization is done.
Using a ROM to implement an n-input function requires:
An n-to-2n decoder, with n inverters and 2n n-input AND gates.
An OR gate with up to 2n inputs.
The number of gates roughly doubles for each additional ROM input.
A programmable logic array, or PLA, makes the decoder part of the ROM “programmable” too. Instead of generating all minterms, you can choose which products (not necessarily minterms) to generate.
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53. A blank 3 x 4 x 3 PLA
This is a 3 x 4 x 3 PLA (3 inputs, up to 4 product terms, and 3 outputs), ready to be programmed.
The left part of the diagram replaces the decoder used in a ROM.
Connections can be made in the “AND array” to produce four arbitrary products, instead of 8 minterms as with a ROM.
Those products can then be summed together in the “OR array.”
Inputs
Outputs
AND array
OR array
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54. Regular K-map minimization
The normal K-map approach is to minimize the number of product terms for each individual function.
For our three functions, this would result in a total of six different product terms.
V2 V1 V0
V2 = m(1,2,3,4)
V1 = m(2,6,7)
V0 = m(4,6,7)
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55. PLA minimization
For a PLA, we should minimize the number of product terms for all functions together.
We could express V2, V1 and V0 with just four total products:
V2 = xy’z’ + x’z + x’yz’ V1 = x’yz’ + xy V0 = xy’z’ + xy
V2 = m(1,2,3,4)
V1 = m(2,6,7)
V0 = m(4,6,7)
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56. PLA example
So we can implement these three functions using a 3 x 4 x 3 PLA:
A2 A1 A0
xy’z’ xy
x’z
x’yz’
V2 = m(1,2,3,4) = xy’z’ + x’z + x’yz’
V1 = m(2,6,7) = x’yz’ + xy
V0 = m(4,6,7) = xy’z’ + xy
V2 V1 V0
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57. PLA evaluation
A k x m x n PLA can implement up to n functions of k inputs, each of which must be expressible with no more than m product terms.
Unlike ROMs, PLAs allow you to choose which products are generated.
This can significantly reduce the fan-in (number of inputs) of gates, as well as the total number of gates.
However, a PLA is less general than a ROM. Not all functions may be expressible with the limited number of AND gates in a given PLA.
In terms of memory, a k x m x n PLA has k address lines, and each of the 2k addresses references an n-bit data value.
But again, not all possible data values can be stored.
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58. Functions and memories
ROMs and PLAs give us two more ways to implement functions.
One difference between expressions/circuits and truth tables:
A circuit implies that some calculation has to be done on the inputs in order to arrive at the output. If the same inputs are given again, we have to repeat that calculation.
A truth table lists all possible combinations of inputs and their corresponding outputs. Instead of doing a potentially lengthy calculation, we can just “look up” the result of a function.
The idea behind using a ROM or PLA to implement a function is to “store” the function’s truth table, so we don’t have to do any (well, very little) computation.
This is like “memorization” or “caching” techniques in programming.
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59. Summary There are two main kinds of random access memory.
Static RAM costs more, but the memory is faster. Static RAM is often used to implement cache memories.
Dynamic RAM costs less and requires less physical space, making it ideal for larger-capacity memories. However, access times are also slower.
ROMs and PLAs are programmable devices that can implement arbitrary functions, which is equivalent to acting as a read-only memory.
ROMs are simpler to program, but contain more gates.
PLAs use less hardware, but it requires some effort to minimize a set of functions. Also, the number of AND gates available can limit the number of expressible functions.
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60. Quizz
You are given
two 1K byte and,
one 2K byte memories.
The word size is 8 bits. Implement a 4K byte memory. k n n
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61. Spring'14
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62. Programmable Logic Devices (PLDs)
PLD is a re-configurable IC built with large numbers of gates connected through electronic fuses to implement arbitrary circuits.
Programmable ROM (Read-Only Memory)
Programmable Logic Array (PLA)
Programmable Array Logic (PAL)
FPGA
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63. PLDs Fixed (decoder) OR array (a) Programmable read-only memory (PROM)
Inputs
Outputs
Fixed
AND array
(decoder)
Programmable
OR array
(a) Programmable read-only memory (PROM)
(b) Programmable array logic (PAL)
(c) Programmable logic array (PLA)
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64. Read-Only Memories (ROMs)
Two dimensional array of 1s and 0s
entry (row) is called a "word"
width of row = word-size
index is called an "address"
address is input
selected word is output
decoder
0 n-1
Address
2 -1 n 1
word[i] = word[j] = 1010
bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches) j i
Internal Organization
word lines (only one is active – decoder is just right for this)
Example:
10-line address x 8 data ROM
210 words x 8 ROM
1024 words x 8 ROM
1k x 8 ROM
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65. ROMs and Combinational Logic
Combinational logic implementation (two- level canonical form) using a ROM
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
A B C F0 F1 F2 F3
Truth Table
Block Diagram
ROM
8 words x 4 bits/word
address
outputs
A B C F0 F1 F2 F3
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66. Memory Array (2n words by m bits)
ROM Structure
n address lines
• • •
inputs
Decoder
2n word lines
outputs
Memory Array (2n words by m bits)
m data lines
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67. Internal Logic of 32x8 ROM 3 . Decoder I0 I1 I2 I3 I4 5 x 32 A7 A6 A51 2 I0 I1 I2 I3 I4 3 . 28 29 30 31
5 x 32
Decoder A7 A6 A5 A4 A3 A2 A1 A0
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68. ROM Content
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69. ROM Programming 3 . Decoder I0 I1 I2 I3 I4 5 x 32 A7 A6 A5 A4 A3 A2 A11 2 I0 I1 I2 I3 I4 3 . 28 29 30 31
5 x 32
Decoder A7 A6 A5 A4 A3 A2 A1 A0
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70. Programmable Logic Array (PLA)
Pre-fabricated building block of many AND/OR gates
Actually NOR or NAND
“Personalized” by making or breaking connections among gates
Programmable array block diagram for sum of products form
• • •
Inputs
AND Array
• • •
Outputs
OR Array
Product Terms
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71. A B C 1 2 3 4 AB AC BC ABC C C B B A A 1 F1 F2 Spring'141 F1 F2
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72. Enabling Concept Shared product terms among outputs Input side:
F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
1 : uncomplemented in term
0 : complemented in term
– : does not participate
Output side:
1 : term connected to output
0 : no connection to output
Personality Matrix
Product Inputs Outputs
Term A B C F0 F1 F2 F3
AB 1 1 – B'C – AC' 1 – B'C' – A 1 – –
reuse of terms
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73. Before Programming
All possible connections available before "programming"
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74. After Programming Unwanted connections are "blown"
Fuse (normally connected, break unwanted ones)
Anti-fuse (normally disconnected, make wanted connections) A B C F1 F2 F3 F0 AB
B'C
AC'
B'C'
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75. Alternate Representation for High Fan-in Structures
Short-hand notation -- don't have to draw all the wires
Signifies a connection is present and perpendicular signal is an input to gate
Notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D A B C D AB
A'B'
CD'
C'D
AB+A'B'
CD'+C'D
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76. Programmable Logic Array Example
Multiple functions of A, B, C
F1 = A B C
F2 = A + B + C
F3 = A' B' C'
F4 = A' + B' + C'
F5 = A xor B xor C
F6 = A xnor B xnor C
full decoder as for memory address
bits stored in memory
A'B'C'
A'B'C
A'BC'
A'BC
AB'C'
AB'C
ABC'
ABC A B C F1 F2 F3 F4 F5 F6
A B C F1 F2 F3 F4 F5 F6
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77. PALs and PLAs Programmable logic array (PLA)
what we've seen so far
unconstrained fully-general AND and OR arrays
Programmable array logic (PAL)
constrained topology of the OR array
innovation by Monolithic Memories
faster and smaller OR plane
a given column of the OR array has access to only a subset of the possible product terms
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78. PALs and PLAs: Design Example
BCD to Gray code converter
X 1
X X X
X X D A B C
X 0
X X X
X X D A B C
A B C D W X Y Z – – – – – 1 1 – – – – – –
K-map for W
K-map for X
X 0
X X X
X X D A B C
X 1
X X X
X X D A B C
Minimized Functions:
W = A + B D + B C
X = B C'
Y = B + C
Z = A’ B’ C’ D + B C D + A D' + B' C D'
K-map for Y
K-map for Z
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79. PALs and PLAs: design example (cont’d)
Code converter: programmed PLA
minimized functions:
W = A + B D + B C
X = B C'
Y = B + C
Z = A'B'C'D + B C D + A D' + B' C D'
A B C D
W X Y Z A BD BC
BC' B C
A'B'C'D
BCD
AD'
BCD'
not a particularly good
candidate for PAL/PLA
implementation since no terms are shared among outputs
however, much more compact and regular implementation when compared with discrete AND and OR gates
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80. PALs and PLAs: design example (cont’d)
Code converter:
programmed PAL
A B C D A BD BC
BC' B C
A'B'C'D
BCD
AD'
B'CD'
W X Y Z
4 product terms per each OR gate
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81. PALs and PLAs: Another Design Example
Magnitude comparator
EQ NE LT GT
A'B'C'D'
A'BC'D
ABCD
AB'CD'
AC'
A'C
B'D
BD'
A'B'D
B'CD
ABC
BC'D'
A B C D D A B C D A B C
K-map for EQ
K-map for NE
EQ =A'B'C'D'+ A'BC'D
+ABCD + AB'CD’
NE = AC'+ B’D + BD’ + A'C D A B C D A B C
K-map for LT
K-map for GT
LT = A'B'D +A'C+B'CD
GT =B C'D'+AC'+ABD'
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82. Programmable Switch Matrix
PLD
PLD
PLD
PLD
I/O
I/O
Programmable Switch Matrix
block
block
PLD
PLD
PLD
PLD
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83. Vertical long line IOB IOB IOB IOB IOB Switch Matrix Switch Matrix
CLB
CLB
Vertical
long line
Switch
Matrix
Switch
Matrix
Switch
Matrix
IOB
IOB
IOB
IOB
IOB
IOB
IOB
Horizontal
long line
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84. Note: Muxes without a select line
C1...C4 H1
DIN/H2
SR/H0 EC
S/R G4 G3 G2 G1
DIN F G H
control
Logic
Function G of
G1 ... G4
D SD YQ Q
ECRD
Logic
Function H
of F , G ,
and H1 G H 1 Y
S/R
DIN F G H
control F4 F3 F2 F1
Logic
Function of
F1 ... F4
D SD Q XQ F H F
EC RD 1 K
(Clock)
Note: Muxes without a select line
are configured by the program memory. X
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85. Configuration Control Write Static RAM Cell Read
Interconnect path
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86. Spring'14
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87. control pull-down I/O Input clock I1 I2 Input Slew rate Passive
pull-up
VCC
pull-down OE
I/O
PAD
D Q O
Output
buffer
Output
clock I1 I2
Input
Input
buffer
Delay
Q D
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88. 32 x 1 Write out n 16 x 2 A[n-1:0] Write row Ram array Read row select
Input register WE
D0 or D1
Write
control
Read
out
SPO
WCLK
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89. 16 x 1 Write D out Read row Write row A[3:0] select RAM array 4
Input register
Read row
16 x 1
RAM array 16
X 1
Write
control
Read
out
SPO 4
WCLK WE D
A[3:0]
DPRA[3:0]
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90. Spring'14
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91. Spring'14
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92. Spring'14
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93. DLL DLL DLL Block Select RAM Block Select RAM CLBs CLBs
I/O I/O I/O I/O I/O I/O
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94. Carry and Logic Lookup O F1 BX CIN CE BY SR XB X COUT YB Y D Q R CK EC
D S Q
Carry
and
Control
Logic I1 F4 F3 F2 G4 G3 G2 G1 I4
Lookup
I3 Table O I2 F1 BX
CIN
CLK CE
F5IN BY SR XB X XQ YQ
Logic Cell
COUT YB Y
AAHFUYS0
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95. TFF SR I/O Bias & SR OFF output buffer I SR IFF input buffer External
D Q SR
VCCO
TFF CK
Package Pin
CLK
VCC OE
TCE SR EC
I/O
Package Pin
Programmable
Bias &
ESD Network O
D Q SR
OFF CK
Programmable
output buffer
Internal
Reference
OCE EC
Programmable IQ
Delay
I/O I
ICE SR
IFF CK EC
D Q
Package Pin
Programmable
input buffer
To Other
External
To Next
I/O
VREF
Inputs of
Banks
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96. CLBs DCM: Clock Manager CLBs Global Clock Mux IOB DCM DCM
Block Select RAM
Multiplier
Block Select RAM
Multiplier
CLBs
CLBs
Block Select RAM
Multiplier
Block Select RAM
Multiplier
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97. IOB Reg DDR mux OCK1 Input ICK1 3-State ICK2 PAD OCK2 Spring'14
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98. 20 D1 D2 D3 D4 D5 D6
100
101 21 22 23 24 25 /1 /2 /3 /4 /5
ROM
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99. Spring'14
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